---
title: "Short note: DE-MUX tree"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:short-note-demux-tree"
source: https://www.bctengineer.com/q/semester_3/digital_logic/short-note-demux-tree
site: BCT Engineering
---

# Short note: DE-MUX tree

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2074 Asoj, 3 marks
- Video: [Design of Demultiplexer Tree](https://www.youtube.com/watch?v=oVUC67G3Xa4) — WIT Solapur - Professional Learning Community
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/short-note-demux-tree
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Write a short note on DE-MUX tree.

## Short answer

A DEMUX tree builds a larger demultiplexer by cascading smaller ones in levels. The first level uses higher-order select bits, and lower levels use lower-order bits. No extra gates are needed, but propagation delay increases with levels.

## Answer

A **DEMUX tree** is a large demultiplexer formed by connecting smaller demultiplexers in two or more levels. It is used when a DEMUX of the required size is not available as one IC.

**Principle:** the first-level DEMUX receives the data input and is driven by the **higher-order** select bits; each of its outputs feeds a second-level DEMUX driven by the **lower-order** select bits. Number of outputs = product of the outputs of each level.

**Example: 1:16 DEMUX from five 1:4 DEMUXes**

```text
                      S1 S0
         S3 S2     +-->[1:4]-- Y0..Y3
       +-------+   |
  D -->|  1:4  |---+-->[1:4]-- Y4..Y7
       | DEMUX |---+
       +-------+   +-->[1:4]-- Y8..Y11
                   |
                   +-->[1:4]-- Y12..Y15
```

If $S_3S_2S_1S_0 = 0110$, the first DEMUX sends D to the second DEMUX (group 01), which sends it to its output 2, i.e. $Y_6$.

**Features:**
- No extra gates are needed; only select lines are shared.
- Other sizes: 1:32 from 1:8 and 1:4 (or 1:2), 1:8 from 1:2 DEMUXes, etc.
- Delay increases with the number of levels.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is a DEMUX tree used?
   A. To increase speed
   B. When a DEMUX of the required size is not available as one IC
   C. To store data
   D. To remove select lines
   Answer: B. Smaller DEMUXes in levels form a larger one. (Key point: Purpose of DEMUX tree)

2. Which select bits drive the first-level DEMUX of the tree?
   A. Lower-order bits
   B. Higher-order bits
   C. Any bits at random
   D. The data bits
   Answer: B. The first level uses higher-order selects; the second level uses the lower-order bits. (Key point: Select bit principle)

3. In the 1:16 tree, for S3S2S1S0 = 0110, where does D appear?
   A. Y4
   B. Y5
   C. Y9
   D. Y6
   Answer: D. S3S2 = 01 picks the second DEMUX (Y4-Y7) and S1S0 = 10 picks its output 2, giving Y6. (Key point: Worked example)

4. Which is true of a DEMUX tree?
   A. Number of outputs is the product of outputs at each level; delay grows with levels
   B. Number of outputs is the sum of outputs at each level
   C. It needs extra AND gates for every level
   D. Delay decreases with levels
   Answer: A. Outputs multiply (4 x 4 = 16), no extra gates are needed, but each level adds delay. (Key point: Features)

## Related in Digital Logic

- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4
- [Short note: MUX tree](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashort-note-mux-tree) — Digital Logic, chapter 4
- [32:1 MUX tree from 4:1; implement Σ(0,1,3,8,9,13)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function) — Digital Logic, chapter 4
- [Multiplexer tree; 16:1 MUX from 4:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-4to1) — Digital Logic, chapter 4