--- title: "SIPO register with 1001 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:sipo-1001-store-retrieve" source: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1001-store-retrieve site: BCT Engineering --- # SIPO register with 1001 data Digital Logic · Chapter 7: Registers - Asked in: 2080 Bhadra, 6 marks - Video: [Shift Register (SIPO & PIPO Mode)](https://www.youtube.com/watch?v=HGFGQ3D3iJ8) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1001-store-retrieve - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question You are provided with a bit sequence 1001 to operate with serial in parallel out shift register. Draw the circuit diagram and timing diagram to illustrate the procedure for storing and retrieving those bits. ## Short answer Input 1001 is applied LSB-first (1,0,0,1) over four clocks. After clock 4 the register stores 1001 (QA=1, QB=0, QC=0, QD=1). Retrieval is parallel: all four bits are read simultaneously at that moment, requiring no extra clock. ## Answer In a **serial-in parallel-out (SIPO) shift register**, bits are fed one by one into the first flip-flop and shifted along at every clock; once all bits are in, they are read at the same time from the outputs of all flip-flops. For the 4-bit sequence 1001 we need four D flip-flops with a common clock. #### Circuit ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-+>|D QB|-+>|D QC|-+>|D QD|-+ |> | | |> | | |> | | |> | | +-----+ | +-----+ | +-----+ | +-----+ | ^ | ^ | ^ | ^ | CLK ----+----|----+----|----+----|----+ | v v v v QA QB QC QD (parallel outputs read together) ``` Each flip-flop's Q drives the next D input, and **all four Q outputs are brought out**. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. #### Operation with data 1001 The register is first cleared (0000). The data is applied **LSB first**, so the serial input is 1, 0, 0, 1 at clocks 1 to 4. | CLK | Serial in | QA | QB | QC | QD | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | | 2 | 0 | 0 | 1 | 0 | 0 | | 3 | 0 | 0 | 0 | 1 | 0 | | 4 | 1 | 1 | 0 | 0 | 1 | | 5 | 0 | 0 | 1 | 0 | 0 | | 6 | 0 | 0 | 0 | 1 | 0 | | 7 | 0 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 | 0 | - **Storing:** after the 4th clock, QA QB QC QD = 1001, which is 1001 with QA as MSB. - **Retrieving:** the four outputs are read **at once (in parallel)** right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.) #### Timing diagram ```text 1 2 3 4 5 6 7 8 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Din ‾‾‾|_______|‾‾‾|________________ QA _|‾‾‾|_______|‾‾‾|______________ QB _____|‾‾‾|_______|‾‾‾|__________ QC _________|‾‾‾|_______|‾‾‾|______ QD _____________|‾‾‾|_______|‾‾‾|__ ``` So **storing** 1001 takes 4 clock pulses (input 1, 0, 0, 1, since 1001 is the same read either way), and **retrieving** is done in one step by reading QA QB QC QD = 1001 in parallel. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many clock pulses store 1001 in a 4-bit SIPO? A. 1 B. 4 C. 2 D. 8 Answer: B. One bit enters per clock, so 4 bits need 4 clocks. (Key point: Storing) 2. How are the bits retrieved? A. By 4 more clocks at QD B. By pulsing a load line C. In one step by reading QA QB QC QD in parallel D. By reversing the shift direction Answer: C. All outputs are available together. (Key point: Retrieving) 3. After clock 3 of storing 1001, what are QA QB QC QD? A. 0100 B. 1001 C. 1000 D. 0010 Answer: D. Input 1, 0, 0 gives 1000, 0100, then 0010. (Key point: Register state) ## Related in Digital Logic - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [4-bit SIPO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-serial-in-serial-out) — Digital Logic, chapter 7, asked 2× - [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2× - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7 ## Related in other subjects - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3 - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6 - [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4 - [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2