--- title: "SIPO with 1010 data up to 9th clock" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:sipo-1010-ninth-clock" source: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1010-ninth-clock site: BCT Engineering --- # SIPO with 1010 data up to 9th clock Digital Logic · Chapter 7: Registers - Asked in: 2082 Shrawan, 3+4 marks - Video: [SIPO Shift Register: Basics, Circuit, Designing, Working, Waveforms and Applications](https://www.youtube.com/watch?v=BcEhle8ev_4) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1010-ninth-clock - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question How does serial-in parallel-out (SIPO) shift register function with neat circuit diagram? Show the 1010 data shift mechanism in the timing diagram with up to 9th clock cycles. ## Short answer With serial input 1010 (LSB first), after 4 clocks the SIPO register holds QA..QD = 1010, ready for parallel readout. At clocks 5–7, QD outputs the stored bits serially as 0,1,0,1; all flip-flops clear by clock 8. Clock 9 shows all outputs at 0, with no new data entered. ## Answer A **serial-in parallel-out (SIPO) shift register** takes data serially, one bit per clock pulse, into the first flip-flop and shifts it along the chain; the outputs of all flip-flops are available together, so after n clocks an n-bit word can be read in parallel. #### Circuit ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-+>|D QB|-+>|D QC|-+>|D QD|-+ |> | | |> | | |> | | |> | | +-----+ | +-----+ | +-----+ | +-----+ | ^ | ^ | ^ | ^ | CLK ----+----|----+----|----+----|----+ | v v v v QA QB QC QD (parallel outputs read together) ``` Four D flip-flops share a common clock. $D_A = D_{in}$, $D_B = Q_A$, $D_C = Q_B$, $D_D = Q_C$, so at every rising edge each stored bit moves one stage right, and QA..QD are taken out as parallel outputs. **Function:** 1. Clear the register (0000). 2. Apply the bits at Din, one per clock, LSB first. 3. After 4 clocks the word sits in QA QB QC QD and is read at once. 4. Further clocks (with Din = 0) push the data out through QD and the register clears. #### Shift mechanism for 1010 (up to 9 clocks) Serial input = 0, 1, 0, 1 at clocks 1 to 4 (1010 LSB first), and 0 afterwards. | CLK | Serial in | QA | QB | QC | QD | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 0 | 0 | | 3 | 0 | 0 | 1 | 0 | 0 | | 4 | 1 | 1 | 0 | 1 | 0 | | 5 | 0 | 0 | 1 | 0 | 1 | | 6 | 0 | 0 | 0 | 1 | 0 | | 7 | 0 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 | 0 | | 9 | 0 | 0 | 0 | 0 | 0 | - **Clock 4:** QA QB QC QD = 1010: the word 1010 is stored and read in parallel. - **Clocks 5 to 8:** the data moves out through QD. QD after clocks 4, 5, 6, 7 is 0, 1, 0, 1 (1010 read LSB first), and the register is clear after clock 8. - **Clock 9:** all outputs remain 0000 since only 0s are entering. #### Timing diagram ```text 1 2 3 4 5 6 7 8 9 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Din ___|‾‾‾|___|‾‾‾|____________________ QA _____|‾‾‾|___|‾‾‾|__________________ QB _________|‾‾‾|___|‾‾‾|______________ QC _____________|‾‾‾|___|‾‾‾|__________ QD _________________|‾‾‾|___|‾‾‾|______ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What happens at clocks 5 to 8 with Din = 0? A. The word stays stored B. The data shifts left C. The word is inverted D. The data moves out through QD and the register clears Answer: D. Each clock shifts right, with zeros entering QA. (Key point: Data flush) 2. What are the outputs at clock 9? A. 0000, since only 0s have entered B. 1010 C. 0101 D. 1111 Answer: A. The register was already clear after clock 8. (Key point: Clock 9) 3. After clock 6, what are QA QB QC QD? A. 0101 B. 0010 C. 0100 D. 1010 Answer: B. Clock 4 gives 1010, clock 5 gives 0101, clock 6 gives 0010. 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