--- title: "4-bit SIPO register with 1010 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:sipo-1010-serial-in-serial-out" source: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1010-serial-in-serial-out site: BCT Engineering --- # 4-bit SIPO register with 1010 data Digital Logic · Chapter 7: Registers - Asked in: 2080 Baisakh, 7 marks - Video: [SIPO Shift Register: Basics, Circuit, Designing, Working, Waveforms and Applications](https://www.youtube.com/watch?v=BcEhle8ev_4) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1010-serial-in-serial-out - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain the operation of 4 bit serial in serial out (SIPO) register with timing diagrams for the given data pattern 1010. ## Short answer A 4-bit SIPO register, when clocked continuously, also provides serial output at QD. With 1010 input LSB first, after four clocks parallel outputs read 1010; additional clocks output 0,1,0,1 from QD. The timing diagram captures both parallel load and serial-out phases. ## Answer The question names the register SIPO, so it is explained here as a 4-bit **serial-in parallel-out** shift register. It accepts data one bit per clock at a single serial input and gives the whole word on four parallel outputs QA to QD. Its last output QD also works as a serial output, so the same circuit acts as a SISO register when the bits are taken out from QD by further clocks. #### Circuit ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-+>|D QB|-+>|D QC|-+>|D QD|-+ |> | | |> | | |> | | |> | | +-----+ | +-----+ | +-----+ | +-----+ | ^ | ^ | ^ | ^ | CLK ----+----|----+----|----+----|----+ | v v v v QA QB QC QD (parallel outputs read together) ``` Each flip-flop's Q drives the next D input, and **all four Q outputs are brought out**. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. #### Operation with data 1010 The register is first cleared (0000). The data is applied **LSB first**, so the serial input is 0, 1, 0, 1 at clocks 1 to 4. | CLK | Serial in | QA | QB | QC | QD | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 0 | 0 | | 3 | 0 | 0 | 1 | 0 | 0 | | 4 | 1 | 1 | 0 | 1 | 0 | | 5 | 0 | 0 | 1 | 0 | 1 | | 6 | 0 | 0 | 0 | 1 | 0 | | 7 | 0 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 | 0 | - **Storing:** after the 4th clock, QA QB QC QD = 1010, which is 1010 with QA as MSB. - **Retrieving:** the four outputs are read **at once (in parallel)** right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.) #### Timing diagram ```text 1 2 3 4 5 6 7 8 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Din ___|‾‾‾|___|‾‾‾|________________ QA _____|‾‾‾|___|‾‾‾|______________ QB _________|‾‾‾|___|‾‾‾|__________ QC _____________|‾‾‾|___|‾‾‾|______ QD _________________|‾‾‾|___|‾‾‾|__ ``` Note the serial output at QD after clocks 4, 5, 6, 7: 0, 1, 0, 1 (1010 read LSB first), which is the serial-out mode of the same register. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How can the SIPO register act as a SISO register? A. Connect the outputs to the inputs B. Disable the clock C. Take the bits from QD while clocking further D. Load the bits in parallel Answer: C. QD is the last stage, so with extra clocks the data comes out serially there. (Key point: SISO mode) 2. What is the QD output after clocks 4, 5, 6, 7 for data 1010? A. 1, 0, 1, 0 B. 0, 0, 1, 1 C. 1, 1, 0, 0 D. 0, 1, 0, 1 Answer: D. 1010 comes out LSB first, so 0, 1, 0, 1. (Key point: Serial output) 3. When does the register become 0000 again with 0s fed in? A. After clock 8 B. After clock 4 C. After clock 5 D. After clock 6 Answer: A. Four clocks load, then four more shift the bits out. (Key point: Emptying) ## Close variants set in other exams - [SISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1101-data) — Digital Logic, chapter 7, asked 10× ## Related in Digital Logic - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [SIPO with 1010 data up to 9th clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-ninth-clock) — Digital Logic, chapter 7 - [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2× - [SIPO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1001-store-retrieve) — Digital Logic, chapter 7 - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [PISO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1010-data) — Digital Logic, chapter 7 ## Related in other subjects - [Pattern lobes and 180° out-of-phase array](https://www.bctengineer.com/question.md?key=semester_6%2Fpropagation_and_antenna%3Alobes-importance-opposite-phase-array) — Propagation and Antenna, chapter 2 - [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2 - [Error detection in serial data transmission](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-error-detection) — Instrumentation II, chapter 3, asked 2× - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2