--- title: "SIPO register with 1101 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:sipo-1101-data" source: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1101-data site: BCT Engineering --- # SIPO register with 1101 data Digital Logic · Chapter 7: Registers - Asked in: 2079 Bhadra, 6 marks; 2076 Chaitra, 6 marks (asked 2 times) - Video: [Shift Register (SIPO & PIPO Mode)](https://www.youtube.com/watch?v=HGFGQ3D3iJ8) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-1101-data - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain the serial in parallel-out (SIPO) shift register with timing diagram of 1101 data input. ## Short answer A 4-bit SIPO shift register receives data bits serially LSB first and presents them in parallel. With input 1101, after four clocks parallel outputs QA QB QC QD become 1101. The timing diagram shows serial input waveform and progressive shifting of each output until the word is complete. ## Answer A **serial-in parallel-out (SIPO) shift register** receives data bit by bit on one input line and presents the complete word on separate parallel output lines. A 4-bit SIPO register is made of four D flip-flops in cascade with a common clock; Q of every stage is an output. #### Circuit ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-+>|D QB|-+>|D QC|-+>|D QD|-+ |> | | |> | | |> | | |> | | +-----+ | +-----+ | +-----+ | +-----+ | ^ | ^ | ^ | ^ | CLK ----+----|----+----|----+----|----+ | v v v v QA QB QC QD (parallel outputs read together) ``` Each flip-flop's Q drives the next D input, and **all four Q outputs are brought out**. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. #### Operation with data 1101 The register is first cleared (0000). The data is applied **LSB first**, so the serial input is 1, 0, 1, 1 at clocks 1 to 4. | CLK | Serial in | QA | QB | QC | QD | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | | 2 | 0 | 0 | 1 | 0 | 0 | | 3 | 1 | 1 | 0 | 1 | 0 | | 4 | 1 | 1 | 1 | 0 | 1 | | 5 | 0 | 0 | 1 | 1 | 0 | | 6 | 0 | 0 | 0 | 1 | 1 | | 7 | 0 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 | 0 | - **Storing:** after the 4th clock, QA QB QC QD = 1101, which is 1101 with QA as MSB. - **Retrieving:** the four outputs are read **at once (in parallel)** right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.) #### Timing diagram ```text 1 2 3 4 5 6 7 8 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Din ‾‾‾|___|‾‾‾‾‾‾‾|________________ QA _|‾‾‾|___|‾‾‾‾‾‾‾|______________ QB _____|‾‾‾|___|‾‾‾‾‾‾‾|__________ QC _________|‾‾‾|___|‾‾‾‾‾‾‾|______ QD _____________|‾‾‾|___|‾‾‾‾‾‾‾|__ ``` SIPO registers convert serial data into parallel form (serial-to-parallel converter), as in a serial receiver. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What serial input applies 1101 at clocks 1 to 4? A. 1, 1, 0, 1 B. 1, 0, 1, 0 C. 0, 1, 0, 1 D. 1, 0, 1, 1 Answer: D. The data is applied LSB first, so 1101 becomes 1, 0, 1, 1. (Key point: Input order) 2. After clock 2, what are QA QB QC QD? A. 0100 B. 1010 C. 0010 D. 1000 Answer: A. After clock 1 it is 1000; clock 2 shifts that right and brings in 0, giving 0100. (Key point: Register state) 3. What is the SIPO register mainly used for? A. Parallel-to-serial conversion B. Serial-to-parallel conversion C. Storing without shifting D. Dividing the clock frequency Answer: B. It receives bits serially and presents the whole word in parallel, as in a serial receiver. (Key point: Application) ## Related in Digital Logic - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× - [SISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1101-data) — Digital Logic, chapter 7, asked 10× - [SIPO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1001-store-retrieve) — Digital Logic, chapter 7 - [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7 - [4-bit SIPO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-serial-in-serial-out) — Digital Logic, chapter 7, asked 2× ## Related in other subjects - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3 - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6 - [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4 - [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2