---
title: "SIPO register with timing diagram"
subject: "Digital Logic"
chapter: 7
key: "semester_3/digital_logic:sipo-generic-timing"
source: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-generic-timing
site: BCT Engineering
---

# SIPO register with timing diagram

Digital Logic · Chapter 7: Registers

- Asked in: 2079 Baisakh, 4 marks; 2075 Asoj, 4 marks (asked 2 times)
- Video: [Shift Register (SIPO & PIPO Mode)](https://www.youtube.com/watch?v=HGFGQ3D3iJ8) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/sipo-generic-timing
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7

## Question

Explain the operation of 4 bit serial in parallel out (SIPO) register with timing diagram.

## Short answer

A 4-bit SIPO shift register uses four cascaded D flip-flops with a common clock. Data is applied serially LSB first; after four clock pulses, all four bits appear simultaneously on parallel outputs QA to QD. For data 1010, outputs become 1010 after clock 4, as shown in timing diagram.

## Answer

A **serial-in parallel-out (SIPO) shift register** takes data serially, one bit per clock, and makes all stored bits available at the same time on separate output lines. A 4-bit SIPO register is four cascaded D flip-flops with a common clock and an output taken from every flip-flop. The example below uses the data 1010.

#### Circuit

```text
 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)
```

Each flip-flop's Q drives the next D input, and **all four Q outputs are brought out**. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

#### Operation with data 1010

The register is first cleared (0000). The data is applied **LSB first**, so the serial input is 0, 1, 0, 1 at clocks 1 to 4.

| CLK | Serial in | QA | QB | QC | QD |
|---|---|---|---|---|---|
| 0 (initial) | - | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 0 | 0 |
| 3 | 0 | 0 | 1 | 0 | 0 |
| 4 | 1 | 1 | 0 | 1 | 0 |
| 5 | 0 | 0 | 1 | 0 | 1 |
| 6 | 0 | 0 | 0 | 1 | 0 |
| 7 | 0 | 0 | 0 | 0 | 1 |
| 8 | 0 | 0 | 0 | 0 | 0 |

- **Storing:** after the 4th clock, QA QB QC QD = 1010, which is 1010 with QA as MSB.
- **Retrieving:** the four outputs are read **at once (in parallel)** right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

#### Timing diagram

```text
       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|________________
QA    _____|‾‾‾|___|‾‾‾|______________
QB    _________|‾‾‾|___|‾‾‾|__________
QC    _____________|‾‾‾|___|‾‾‾|______
QD    _________________|‾‾‾|___|‾‾‾|__
```

SIPO registers are used for serial-to-parallel conversion, e.g. in a UART receiver.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is the stored word retrieved from a SIPO register?
   A. All four outputs are read at once right after clock 4
   B. Bits are read one by one from QD over 4 more clocks
   C. Only QA is read after clock 4
   D. A load pulse is needed first, then 4 clocks
   Answer: A. All Q outputs are brought out, so reading takes no extra clock. (Key point: Parallel retrieval)

2. At each clock edge in the SIPO register, what does QB take?
   A. The value of Din
   B. The previous value of QA
   C. The previous value of QC
   D. The value of QD
   Answer: B. Each flip-flop's D is the Q of the stage before it: QB <- QA. (Key point: Shift equations)

3. For 1010 the serial input at clocks 1 to 4 is 0, 1, 0, 1. Why?
   A. The data is applied MSB first
   B. The input is inverted
   C. The data is applied LSB first
   D. The register is cleared in between
   Answer: C. 1010 read LSB first is 0, 1, 0, 1. (Key point: Input order)

## Related in Digital Logic

- [4-bit SIPO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-serial-in-serial-out) — Digital Logic, chapter 7, asked 2×
- [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7
- [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9×
- [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2×
- [SIPO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1001-store-retrieve) — Digital Logic, chapter 7
- [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7

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- [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2
- [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4
- [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3
- [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2