--- title: "SISO register with 1011 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:siso-1011-data" source: https://www.bctengineer.com/q/semester_3/digital_logic/siso-1011-data site: BCT Engineering --- # SISO register with 1011 data Digital Logic · Chapter 7: Registers - Asked in: 2081 Bhadra, 2+3 marks; 2078 Bhadra, 3+3 marks; 2074 Asoj, 6 marks (asked 3 times) - Video: [Shift Register (SISO Mode)](https://www.youtube.com/watch?v=unorn9n-UpE) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/siso-1011-data - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain the operation of 4 bit serial in serial out (SISO) register with timing diagram of 1011 data input. ## Short answer A 4-bit SISO register shifts data serially. To store 1011 LSB first, apply Din sequence 1,1,0,1. After clock 4, QA–QD = 1011. Serial output QD yields 1,1,0,1 on clocks 4–7, and the register empties after 8 clocks. ## Answer A **serial-in serial-out (SISO) shift register** takes data one bit at a time at a single input and gives it out one bit at a time at a single output. A 4-bit SISO register is a chain of four D flip-flops (A, B, C, D) driven by a common clock. #### Circuit ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-->|D QB|-->|D QC|-->|D QD|--> Dout |> | |> | |> | |> | +-----+ +-----+ +-----+ +-----+ ^ ^ ^ ^ CLK ----+---------+---------+---------+ ``` Data enters FF-A only and leaves from FF-D only. At each rising edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. #### Operation with data 1011 The register is cleared to 0000 first. The data is entered **LSB first**: serial input = 1, 1, 0, 1 at clocks 1 to 4, then 0s. | CLK | Serial in | QA | QB | QC | QD (out) | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 1 | 0 | 0 | | 3 | 0 | 0 | 1 | 1 | 0 | | 4 | 1 | 1 | 0 | 1 | 1 | | 5 | 0 | 0 | 1 | 0 | 1 | | 6 | 0 | 0 | 0 | 1 | 0 | | 7 | 0 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 | 0 | - **Storing (clocks 1 to 4):** after clock 4, QA QB QC QD = 1011, i.e. 1011 is held with QA as MSB. - **Retrieving (serial out at QD):** the output after clocks 4, 5, 6, 7 is 1, 1, 0, 1, which is 1011 read LSB first. After clock 8 the register is empty again. - A 4-bit SISO register needs 4 clocks to load and 4 clocks to empty (3 more clocks after the first bit appears). #### Timing diagram ```text 1 2 3 4 5 6 7 8 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Din ‾‾‾‾‾‾‾|___|‾‾‾|________________ QA _|‾‾‾‾‾‾‾|___|‾‾‾|______________ QB _____|‾‾‾‾‾‾‾|___|‾‾‾|__________ QC _________|‾‾‾‾‾‾‾|___|‾‾‾|______ QD _____________|‾‾‾‾‾‾‾|___|‾‾‾|__ ``` Each Q waveform is the previous one delayed by one clock period. Uses: time delay of n clock periods (digital delay line) and serial data transfer. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In a 4-bit SISO register, where does data enter and leave? A. Enters FF-A only and leaves from FF-D only B. Enters every flip-flop together and leaves from FF-D C. Enters FF-A and leaves from every flip-flop together D. Enters FF-D and leaves from FF-A Answer: A. Serial input goes only to the first flip-flop (A) and the output is taken only from the last (D). (Key point: Data path) 2. For the data 1011, what is the serial input at clocks 1 to 4? A. 1, 0, 1, 1 (MSB first) B. 1, 1, 0, 1 (LSB first) C. 0, 1, 1, 0 D. 1, 1, 1, 0 Answer: B. The answer enters the data LSB first, so 1011 is applied as 1, 1, 0, 1. (Key point: Input order) 3. After the 4th clock, what are QA QB QC QD? A. 1101 B. 0000 C. 1011 D. 1111 Answer: C. After four shifts the first bit applied has reached QD, so the word 1011 is held with QA as MSB. (Key point: Stored word) 4. How many clocks does a 4-bit SISO need to load and to empty? A. 1 to load and 4 to empty B. 4 to load and 1 to empty C. 1 to load and 1 to empty D. 4 to load and 4 to empty Answer: D. Data moves one stage per clock, so loading and emptying both take 4 clocks. (Key point: Serial output and timing) ## Close variants set in other exams - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× - [SISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1101-data) — Digital Logic, chapter 7, asked 10× ## Related in Digital Logic - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [4-bit SIPO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-serial-in-serial-out) — Digital Logic, chapter 7, asked 2× - [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4× - [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2× - [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7 ## Related in other subjects - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [4-bit R-2R ladder bit voltages and 1011 output](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ar2r-4bit-12v-1011) — Advanced Electronics, chapter 3 - [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6× - [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2