--- title: "SISO register with 1101 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:siso-1101-data" source: https://www.bctengineer.com/q/semester_3/digital_logic/siso-1101-data site: BCT Engineering --- # SISO register with 1101 data Digital Logic · Chapter 7: Registers - Asked in: 2081 Baisakh, 6 marks - Video: [Shift Register (SISO Mode)](https://www.youtube.com/watch?v=unorn9n-UpE) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/siso-1101-data - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain the operation of 4 bit serial-in-serial out (SISO) register with timing diagram for the given data pattern 1101. ## Short answer Data 1101 is loaded LSB-first into a 4-bit SISO register over four clocks, storing 1101 (QA=1,QB=1,QC=0,QD=1) after clock 4. Serial output at QD produces 1,0,1,1 over clocks 5–8. Loading takes 4 pulses; reading out takes 4 pulses, with the first bit appearing at clock 5. ## Answer A **4-bit serial-in serial-out (SISO) shift register** is four D flip-flops connected in a chain with a common clock. Data enters one bit per clock at the first flip-flop and comes out one bit per clock from the last flip-flop. #### Circuit ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-->|D QB|-->|D QC|-->|D QD|--> Dout |> | |> | |> | |> | +-----+ +-----+ +-----+ +-----+ ^ ^ ^ ^ CLK ----+---------+---------+---------+ ``` Data enters FF-A only and leaves from FF-D only. At each rising edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. #### Operation with data 1101 The register is cleared to 0000 first. The data is entered **LSB first**: serial input = 1, 0, 1, 1 at clocks 1 to 4, then 0s. | CLK | Serial in | QA | QB | QC | QD (out) | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | | 2 | 0 | 0 | 1 | 0 | 0 | | 3 | 1 | 1 | 0 | 1 | 0 | | 4 | 1 | 1 | 1 | 0 | 1 | | 5 | 0 | 0 | 1 | 1 | 0 | | 6 | 0 | 0 | 0 | 1 | 1 | | 7 | 0 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 | 0 | - **Storing (clocks 1 to 4):** after clock 4, QA QB QC QD = 1101, i.e. 1101 is held with QA as MSB. - **Retrieving (serial out at QD):** the output after clocks 4, 5, 6, 7 is 1, 0, 1, 1, which is 1101 read LSB first. After clock 8 the register is empty again. - A 4-bit SISO register needs 4 clocks to load and 4 clocks to empty (3 more clocks after the first bit appears). #### Timing diagram ```text 1 2 3 4 5 6 7 8 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Din ‾‾‾|___|‾‾‾‾‾‾‾|________________ QA _|‾‾‾|___|‾‾‾‾‾‾‾|______________ QB _____|‾‾‾|___|‾‾‾‾‾‾‾|__________ QC _________|‾‾‾|___|‾‾‾‾‾‾‾|______ QD _____________|‾‾‾|___|‾‾‾‾‾‾‾|__ ``` Each Q waveform is the previous one delayed by one clock period. Uses: delaying a serial signal by 4 clock periods and serial data transfer. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What serial input applies 1101 at clocks 1 to 4? A. 1, 1, 0, 1 B. 0, 1, 0, 1 C. 1, 0, 1, 1 D. 1, 0, 1, 0 Answer: C. LSB first. (Key point: Input order) 2. What is QD after clocks 4, 5, 6, 7? A. 1, 1, 0, 1 B. 0, 1, 1, 0 C. 1, 0, 0, 1 D. 1, 0, 1, 1 Answer: D. 1101 emerges LSB first as 1, 0, 1, 1. (Key point: Serial output) 3. What does a 4-bit SISO do to a serial signal? A. Delays it by 4 clock periods B. Converts it to parallel C. Inverts it D. Doubles its speed Answer: A. Each Q waveform is the previous one delayed by one period. (Key point: Delay) ## Close variants set in other exams - [4-bit SIPO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-serial-in-serial-out) — Digital Logic, chapter 7, asked 2× - [SISO register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1011-data) — Digital Logic, chapter 7, asked 9× - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× ## Related in Digital Logic - [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2× - [PISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1101-data) — Digital Logic, chapter 7, asked 2× - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7 - [SIPO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1001-store-retrieve) — Digital Logic, chapter 7 ## Related in other subjects - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6× - [Pattern lobes and 180° out-of-phase array](https://www.bctengineer.com/question.md?key=semester_6%2Fpropagation_and_antenna%3Alobes-importance-opposite-phase-array) — Propagation and Antenna, chapter 2 - [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2