---
title: "SISO shift register with timing diagram"
subject: "Digital Logic"
chapter: 7
key: "semester_3/digital_logic:siso-generic-timing"
source: https://www.bctengineer.com/q/semester_3/digital_logic/siso-generic-timing
site: BCT Engineering
---

# SISO shift register with timing diagram

Digital Logic · Chapter 7: Registers

- Asked in: 2080 Bhadra, 4+2 marks; 2076 Asoj; 2074 Chaitra, 5 marks; 2069 Chaitra, 4 marks; 2068 Chaitra, 4 marks (asked 5 times)
- Video: [Shift Register (SISO Mode)](https://www.youtube.com/watch?v=unorn9n-UpE) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/siso-generic-timing
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7

## Question

Explain the operation of 4 bit serial in serial out (SISO) register with timing diagram.

## Short answer

A 4-bit SISO register is a chain of four D flip-flops. Data enters serially at Din and shifts right each clock. To store 1011 LSB first, apply 1,1,0,1 on clocks 1–4; after clock 4, QA–QD = 1011 (QA=MSB). Serial output QD then produces 1,1,0,1 on clocks 4–7, and the register empties after 8 clocks.

## Answer

A **serial-in serial-out (SISO) shift register** accepts data one bit at a time on a single input line and delivers it one bit at a time from the last flip-flop. A 4-bit SISO register is four D flip-flops in cascade with a common clock.

#### Circuit

```text
 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+
```

The Q output of each flip-flop drives the D input of the next, so at every clock edge each bit moves one place to the right: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

#### Operation (example: storing 1011)

Assume the register is cleared (all 0) and the data 1011 is entered **LSB first**, so the serial input sequence is 1, 1, 0, 1 on clocks 1 to 4. After clock 4 the word is fully stored; clocks 5 to 8 (with input 0) shift it out at QD.

| CLK | Serial in | QA | QB | QC | QD (out) |
|---|---|---|---|---|---|
| 0 (initial) | - | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 |
| 2 | 1 | 1 | 1 | 0 | 0 |
| 3 | 0 | 0 | 1 | 1 | 0 |
| 4 | 1 | 1 | 0 | 1 | 1 |
| 5 | 0 | 0 | 1 | 0 | 1 |
| 6 | 0 | 0 | 0 | 1 | 0 |
| 7 | 0 | 0 | 0 | 0 | 1 |
| 8 | 0 | 0 | 0 | 0 | 0 |

- **Storing (clocks 1-4):** after 4 clocks QA QB QC QD = 1011, i.e. the number 1011 with QA as MSB.
- **Retrieving:** the LSB appears at QD after clock 4, and clocks 5, 6 and 7 bring out the remaining bits. An n-bit word takes n clocks to load; since the first bit is then already at the output, n - 1 more clocks read out the rest (n more clocks empty the register).

#### Timing diagram

```text
       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾‾‾‾‾|___|‾‾‾|________________
QA    _|‾‾‾‾‾‾‾|___|‾‾‾|______________
QB    _____|‾‾‾‾‾‾‾|___|‾‾‾|__________
QC    _________|‾‾‾‾‾‾‾|___|‾‾‾|______
QD    _____________|‾‾‾‾‾‾‾|___|‾‾‾|__
```

Each waveform is the one above it delayed by one clock period. SISO registers are used as **digital delay lines** (delay = n clock periods) and for serial data transmission.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is a 4-bit SISO register built?
   A. Four D flip-flops in cascade with a common clock, each Q driving the next D
   B. Four flip-flops with separate clocks
   C. One flip-flop with four outputs
   D. Four S-R latches with no clock
   Answer: A. The Q of each D flip-flop feeds the D of the next, so bits move one place per clock. (Key point: Structure)

2. At each clock edge, what happens to the stored bits?
   A. All bits clear
   B. Every bit moves one place right (QB gets QA, QC gets QB, and so on)
   C. All bits load in parallel
   D. Only QA changes and others hold
   Answer: B. QA gets Din, QB gets QA, QC gets QB and QD gets QC. (Key point: Shift action)

3. What is the delay of an n-bit SISO register used as a delay line?
   A. One clock period
   B. n clock periods
   C. n/2 clock periods
   D. Zero
   Answer: B. Each stage delays by one clock, so n stages give n clock periods. (Key point: Delay)

4. After how many clocks is a 4-bit word fully stored?
   A. 1
   B. 2
   C. 4
   D. 8
   Answer: C. One bit enters per clock, so 4 clocks store 4 bits. (Key point: Loading time)

## Close variants set in other exams

- [SISO register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1011-data) — Digital Logic, chapter 7, asked 9×
- [SISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1101-data) — Digital Logic, chapter 7, asked 10×

## Related in Digital Logic

- [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7
- [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7
- [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2×
- [4-bit PISO shift register working](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-generic-circuit) — Digital Logic, chapter 7, asked 2×
- [4-bit bidirectional shift register](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abidirectional-shift-register) — Digital Logic, chapter 7
- [Shift register uses; 4-bit ring counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aring-counter-4bit) — Digital Logic, chapter 7

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