--- title: "SISO and SIPO shift register circuits" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:siso-sipo-circuit" source: https://www.bctengineer.com/q/semester_3/digital_logic/siso-sipo-circuit site: BCT Engineering --- # SISO and SIPO shift register circuits Digital Logic · Chapter 7: Registers - Asked in: 2078 Kartik, 3+4 marks - Video: [Lec - 48: Shift Registers | SISO, SIPO, PISO, PIPO](https://www.youtube.com/watch?v=NjMX4hohyRI) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/siso-sipo-circuit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Draw the circuit diagram of Serial In Serial Out and Serial In Parallel Out shift register and explain one of them. ## Short answer In a Serial In/Serial Out shift register, data enters and leaves one bit at a time through the chain of D flip-flops, providing a 4-clock delay. The Serial In/Parallel Out register instead takes parallel outputs from all flip-flops after 4 clocks, converting serial data to a parallel word. ## Answer Both registers are chains of D flip-flops with a common clock in which Q of one stage drives D of the next. They differ only in how the output is taken. #### Serial In Serial Out (SISO) ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-->|D QB|-->|D QC|-->|D QD|--> Dout |> | |> | |> | |> | +-----+ +-----+ +-----+ +-----+ ^ ^ ^ ^ CLK ----+---------+---------+---------+ ``` Output only from the last flip-flop (QD). #### Serial In Parallel Out (SIPO) ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-+>|D QB|-+>|D QC|-+>|D QD|-+ |> | | |> | | |> | | |> | | +-----+ | +-----+ | +-----+ | +-----+ | ^ | ^ | ^ | ^ | CLK ----+----|----+----|----+----|----+ | v v v v QA QB QC QD (parallel outputs read together) ``` Outputs from every flip-flop (QA to QD) are available together. #### Explanation of SIPO shift register 1. Clear all flip-flops (QA..QD = 0000). 2. Apply the data bits one at a time at Din, LSB first. At each rising clock edge every bit moves one stage to the right: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. 3. After 4 clocks the full word is stored and is read **in parallel** from QA QB QC QD. Example, storing 1011 (serial input 1, 1, 0, 1): | CLK | Serial in | QA | QB | QC | QD | |---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 1 | 0 | 0 | | 3 | 0 | 0 | 1 | 1 | 0 | | 4 | 1 | 1 | 0 | 1 | 1 | ```text 1 2 3 4 CLK _|‾|_|‾|_|‾|_|‾| Din ‾‾‾‾‾‾‾|___|‾‾‾| QA _|‾‾‾‾‾‾‾|___|‾‾ QB _____|‾‾‾‾‾‾‾|__ QC _________|‾‾‾‾‾‾ QD _____________|‾‾ ``` After the 4th clock the outputs show QA QB QC QD = 1011. Thus SIPO converts serial data to parallel form (used in serial receivers), while SISO only delays the data by 4 clock periods. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the difference between SISO and SIPO circuits? A. Only how the output is taken: SISO from QD, SIPO from all QA to QD B. SIPO has twice as many flip-flops C. SISO uses a different clock D. SIPO has no serial input Answer: A. Both are chains of D flip-flops; they differ in output taking. (Key point: SISO vs SIPO) 2. How is the stored word read from the SIPO after 4 clocks? A. Bit by bit at QD B. In parallel from QA QB QC QD C. Only from QA D. After 8 more clocks Answer: B. The word is read at once from all outputs. (Key point: SIPO reading) 3. Storing 1011 (input 1, 1, 0, 1), what is QA QB QC QD after clock 3? A. 1101 B. 1011 C. 0110 D. 0011 Answer: C. After clock 2 it is 1100; clock 3 shifts right and brings in 0, giving 0110. (Key point: Register state) ## Related in Digital Logic - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2× - [SIPO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1001-store-retrieve) — Digital Logic, chapter 7 - [SISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1101-data) — Digital Logic, chapter 7, asked 10× - [SISO register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1011-data) — Digital Logic, chapter 7, asked 9× ## Related in other subjects - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6 - [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4 - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3