--- title: "SR drawbacks; D flip-flop operation" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sr-drawback-d-flipflop" source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-drawback-d-flipflop site: BCT Engineering --- # SR drawbacks; D flip-flop operation Digital Logic · Chapter 6: Flip Flops - Asked in: 2068 Chaitra, 1+7 marks - Video: [Lec -37: Introduction to D Flip Flop | Circuit, Working, Characteristics & Excitation Table](https://www.youtube.com/watch?v=SCZaFD9Zv1s) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-drawback-d-flipflop - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Write down the drawbacks of SR flip flop. Explain the operation of data flip flop with timing diagram and truth table. ## Short answer SR flip-flop has a forbidden S=R=1 state causing non-complementary outputs and unpredictable state when both inputs go low. A D flip-flop avoids this: D connects to S, D' to R, so S and R are always complementary; at each clock edge Q copies D and holds until next edge. ## Answer #### Drawbacks of S-R flip-flop - With **S = R = 1** (both active) both outputs are forced to the same level, so Q and Q' are no longer complements. This input is **forbidden/invalid**. - When S and R return from 1,1 to 0,0 together, the next state depends on which gate is faster, so the output is **unpredictable** (race). - The designer must always make sure S and R are never both 1, which limits its use. (The J-K flip-flop removes this drawback by toggling for J = K = 1.) #### Data (D) flip-flop A **D (data or delay) flip-flop** has a single data input D. At the active clock edge, the value of D is copied to Q and held until the next active edge: $Q_{n+1} = D$. It is built from a clocked S-R flip-flop by connecting D to S and D' to R through an inverter, which removes the invalid state. **Logic diagram** ```text D --+------------>+------+ S* +------+ | | NAND |----->| NAND |---> Q | CLK --+-->| G1 | Q'->| G3 | | | +------+ +------+ | | +------+ R* +------+ | +-->| NAND |----->| NAND |---> Q' +--[NOT]----->| G2 | Q-->| G4 | +------+ +------+ S = D and R = D' : the forbidden S=R=1 never occurs ``` **Graphic symbol** ```text +---------+ D ---| D Q |--- Q CLK -|> | | Q' |--- Q' +---------+ ``` **Operation** 1. **Clock inactive (no edge / CLK = 0):** G1 and G2 outputs are 1, the NAND latch holds the previous state. 2. **D = 1 at the clock:** S = 1, R = 0. G1 output S* = 0 sets the latch: Q = 1. 3. **D = 0 at the clock:** S = 0, R = 1. G2 output R* = 0 resets the latch: Q = 0. 4. S and R are always complements, so the forbidden S = R = 1 state never appears. Because the output follows the input with a delay of one clock, it is also called a **delay flip-flop**; it is the basic element of registers and memory. **Truth table** | CLK | D | Q+ | Action | |---|---|---|---| | no edge | x | Q | No change | | edge | 0 | 0 | Reset | | edge | 1 | 1 | Set | Characteristic equation: $Q_{n+1} = D$. **Timing diagram** (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| D ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾ ``` At every rising edge Q takes the value D had just before that edge (D sequence 1, 1, 0, 1, 0, 0, 1 gives Q = 1, 1, 0, 1, 0, 0, 1); changes of D between edges are ignored. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why is the input S = R = 1 forbidden in an S-R flip-flop? A. It forces both outputs to the same level so Q and Q' are not complements B. It makes the flip-flop toggle on every clock C. It disconnects the clock from the latch D. It resets the flip-flop permanently Answer: A. With S = R = 1 both outputs go to the same level, so Q and Q' stop being complements and the state is invalid. (Key point: S=R=1 forbidden) 2. What happens when S and R go from 1,1 to 0,0 together? A. Q is always set to 1 B. Q is always reset to 0 C. The next state is unpredictable because it depends on which gate is faster D. The previous state is restored Answer: C. The final state depends on gate speeds (a race), so the output is indeterminate. (Key point: Race on release) 3. How is a D flip-flop built from a clocked S-R flip-flop? A. S and R are tied together to D B. D is connected to S and D' (through an inverter) to R C. D is connected to R and S is grounded D. D is connected to the clock input Answer: B. S = D and R = D', so S and R are always complements and S = R = 1 never occurs. (Key point: D connection) 4. At each active clock edge, what does a D flip-flop do with the D input? A. Toggles Q if D = 1 B. Copies D to Q and holds it until the next active edge C. Ignores D and holds Q D. Sets Q to 1 whatever D is Answer: B. Q(n+1) = D, so Q takes the value of D at the edge and holds it. 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