--- title: "SR drawback; edge triggered JK flip-flop" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sr-drawback-edge-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-drawback-edge-jk site: BCT Engineering --- # SR drawback; edge triggered JK flip-flop Digital Logic · Chapter 6: Flip Flops - Asked in: 2074 Chaitra, 2+4 marks - Video: [JK Flip Flop Timing Diagrams](https://www.youtube.com/watch?v=A4sdlfNjves) — Joe Haas - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-drawback-edge-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Write down the drawback of SR Flip-Flop. Explain the operation of edge triggered JK Flip-Flop with timing diagram and truth table. ## Short answer The SR flip-flop’s drawback is the forbidden S=R=1 input, leading to race and unpredictable output. The edge-triggered JK flip-flop solves this by using J and K; at the active clock edge, J=K=1 toggles, while other combinations hold, set, or reset, with no invalid state. ## Answer #### Drawback of S-R flip-flop - With **S = R = 1** (both active) both outputs are forced to the same level, so Q and Q' are no longer complements. This input is **forbidden/invalid**. - When S and R return from 1,1 to 0,0 together, the next state depends on which gate is faster, so the output is **unpredictable** (race). - The designer must always make sure S and R are never both 1, which limits its use. (The J-K flip-flop removes this drawback by toggling for J = K = 1.) #### Edge-triggered J-K flip-flop An edge-triggered J-K flip-flop responds to J and K only at the active (here rising) clock edge. A small edge-detector circuit turns each rising edge into a very narrow pulse CLK* that enables the input gates. ```text CLK --+---------------->+-----+ | | AND |---> CLK* +--->[ NOT ]----->+-----+ (delay dt) CLK* = CLK . CLK'(delayed): a spike of width about dt at every rising edge of CLK ``` ```text +------+ S* +------+ J -------| |----->| | CLK* ----| NAND | | NAND |-----> Q Q' ------| G1 | Q'->| G3 | +------+ +------+ +------+ R* +------+ K -------| |----->| | CLK* ----| NAND | | NAND |-----> Q' Q ------| G2 | Q-->| G4 | +------+ +------+ G3 and G4 are cross-coupled (NAND latch). Q' is fed back to G1, Q is fed back to G2. ``` **Operation** - **J = K = 0:** G1 and G2 are disabled (output 1), the latch holds: no change. - **J = 0, K = 1:** at the edge G2 gives 0 only if Q = 1, so the flip-flop resets (Q = 0). - **J = 1, K = 0:** at the edge G1 gives 0 only if Q' = 1, so the flip-flop sets (Q = 1). - **J = K = 1:** the gate whose feedback input is 1 fires, so the output toggles. Since CLK* is narrower than the propagation delay, it toggles only once per edge (no race-around). **Truth table** | CLK | J | K | Q+ | Action | |---|---|---|---|---| | no edge | x | x | Q | No change | | edge | 0 | 0 | Q | No change (hold) | | edge | 0 | 1 | 0 | Reset | | edge | 1 | 0 | 1 | Set | | edge | 1 | 1 | Q' | Toggle | **Timing diagram** (output changes only at rising edges; Q starts at 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| J ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾| K _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__ ``` | Edge | J | K | Q before | Q after | Action | |---|---|---|---|---|---| | 1 | 1 | 0 | 0 | 1 | Set | | 2 | 0 | 0 | 1 | 1 | Hold | | 3 | 1 | 1 | 1 | 0 | Toggle | | 4 | 1 | 1 | 0 | 1 | Toggle | | 5 | 0 | 1 | 1 | 0 | Reset | | 6 | 1 | 0 | 0 | 1 | Set | | 7 | 1 | 1 | 1 | 0 | Toggle | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the main drawback of the SR flip-flop? A. It cannot be set B. It has no clock C. It toggles D. S = R = 1 makes both outputs the same level, an invalid input with unpredictable result Answer: D. S = R = 1 breaks the complement relation, and releasing them together is a race. (Key point: SR drawback) 2. How does the JK flip-flop remove this drawback? A. J = K = 1 makes it toggle B. J = K = 1 holds C. It ignores J D. J = K = 0 is disallowed Answer: A. The invalid combination is used for toggling. (Key point: JK fix) 3. With J = 1, K = 0 at the edge and Q = 0, what happens? A. Toggles back B. G1 fires and sets Q = 1 C. G2 resets D. No change Answer: B. G1 has Q' = 1, so it gives 0 and sets the latch. (Key point: Operation) 4. Why does the edge-triggered JK avoid race-around? A. It has no feedback B. K is held 0 C. CLK* is narrower than the propagation delay, so it toggles once per edge D. The clock is slow Answer: C. The pulse ends before the changed output can re-enable the gates. (Key point: No race-around) ## Close variants set in other exams - [Edge triggered SR flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-sr-flipflop) — Digital Logic, chapter 6, asked 3× ## Related in Digital Logic - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6 - [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6 - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 - [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6 - [SR drawbacks; D flip-flop operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-d-flipflop) — Digital Logic, chapter 6 ## Related in other subjects - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6 - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6