---
title: "SR equation; mod-5 counter using D flip-flops"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:sr-equation-mod5-d-counter"
source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-equation-mod5-d-counter
site: BCT Engineering
---

# SR equation; mod-5 counter using D flip-flops

Digital Logic · Chapter 8: Counters

- Asked in: 2081 Baisakh, 3+7 marks
- Video: [Digital Electronics: Mod 5 counter using D Flip Flops only](https://www.youtube.com/watch?v=-XtLrskCdkc) — sacademy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-equation-mod5-d-counter
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Find out characteristic equation for SR flip-flop. Design a mod-5 synchronous counter using D flip-flops with negative edge triggering clock system.

## Short answer

SR characteristic: Q+ = S + R'Q, with SR=0. For mod-5 synchronous counter, three negative-edge D flip-flops share the clock. D2 = Q1·Q0, D1 = Q1⊕Q0, D0 = Q2'·Q0'. Counts 000→001→010→011→100→000; unused states lead to valid count.

## Answer

#### Characteristic equation of SR flip-flop
The characteristic equation gives the next state $Q^+$ in terms of the inputs and the present state $Q$.

| S | R | Q | Q+ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | X (invalid) |
| 1 | 1 | 1 | X (invalid) |

| Q+: S / RQ | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | X | X |

Grouping the row S = 1 (with the X cells) gives $S$; grouping cells 01 of both rows gives $\overline{R}Q$:
$$
Q^+ = S + \overline{R}\,Q, \qquad \text{with the condition } SR = 0
$$

#### Mod-5 synchronous counter using D flip-flops (negative-edge clock)
**Step 1:** States 000 → 001 → 010 → 011 → 100 → 000. 3 D flip-flops ($Q_2Q_1Q_0$), all clocked by the falling edge. States 101, 110, 111 are don't cares. For a D flip-flop $D = Q^+$.

**Step 2: Excitation table**
| Present Q2Q1Q0 | Next Q2Q1Q0 | D2 | D1 | D0 |
|---|---|---|---|---|
| 000 | 001 | 0 | 0 | 1 |
| 001 | 010 | 0 | 1 | 0 |
| 010 | 011 | 0 | 1 | 1 |
| 011 | 100 | 1 | 0 | 0 |
| 100 | 000 | 0 | 0 | 0 |

**Step 3: K-maps**

| D0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | X | X | X |

| D1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | X | X | X |

| D2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | X | X | X |

**Step 4: Equations**
$$
\begin{aligned} &D_2 = Q_1Q_0 \\ &D_1 = Q_1\overline{Q_0} + \overline{Q_1}Q_0 \\ &D_0 = \overline{Q_2}\overline{Q_0} \end{aligned}
$$
so $D_1 = Q_1 \oplus Q_0$.

**Step 5: Circuit diagram**
```text
   +-----+       +-----+       +-----+
D0>|D   Q|-Q0 D1>|D   Q|-Q1 D2>|D   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
   |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
D0 = Q2'.Q0'  (NOR of Q2 and Q0)
D1 = Q1 XOR Q0
D2 = Q1.Q0
```

**Step 6: Unused states:** 101 → 010, 110 → 010, 111 → 100, so the counter is self-starting.

**Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|___________|‾‾‾
Q0   ____|‾‾‾|___|‾‾‾|_______|‾‾‾|___
Cnt  0    1   2   3   4   0   1   2
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the characteristic equation of the SR flip-flop?
   A. Q+ = S + R'Q with SR = 0
   B. Q+ = S'R + Q
   C. Q+ = SR + Q'
   D. Q+ = S'Q + R
   Answer: A. From the K-map, Q+ = S + R'Q, valid when the forbidden input S = R = 1 is excluded (SR = 0). (Key point: SR characteristic equation)

2. What is the excitation rule for a D flip-flop?
   A. D = Q XOR Q+
   B. D = Q+
   C. D = Q
   D. D = NOT Q+
   Answer: B. A D flip-flop simply copies its input to the output at the clock edge, so D equals the desired next state. (Key point: D excitation)

3. Which set is the correct result for the mod-5 D-flip-flop counter?
   A. D2 = Q1 + Q0, D1 = Q1Q0, D0 = Q2 Q0
   B. D2 = Q1Q0, D1 = Q1 XOR Q0, D0 = Q2'Q0'
   C. D2 = Q2Q1, D1 = Q1 XOR Q0, D0 = Q0'
   D. D2 = Q1Q0, D1 = Q1Q0', D0 = Q2'Q0
   Answer: B. D2 = 1 only for 011, D1 toggles pattern 01/10 giving the XOR, and D0 = 1 for 000 and 010, giving Q2'Q0'. (Key point: Mod-5 D equations)

4. What happens to the unused state 111 in the mod-5 D counter?
   A. It goes to 000
   B. It stays at 111
   C. It goes to 100
   D. It goes to 010
   Answer: C. With D2 = Q1Q0 = 1, D1 = 1 XOR 1 = 0, D0 = 0, the next state is 100, a valid state. (Key point: Self-starting check)

## Related in Digital Logic

- [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4×
- [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8
- [Mod-5 synchronous up counter using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-sr) — Digital Logic, chapter 8, asked 5×
- [Mod-5 Gray code synchronous up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-gray-sync-counter) — Digital Logic, chapter 8
- [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×

## Related in other subjects

- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
