--- title: "SR flip-flop diagram, excitation table, equation" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sr-flipflop-diagram-equation" source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-flipflop-diagram-equation site: BCT Engineering --- # SR flip-flop diagram, excitation table, equation Digital Logic · Chapter 6: Flip Flops - Asked in: 2080 Bhadra, 1+2+3 marks - Video: [Truth Table, Characteristic Table and Excitation Table for SR Flip Flop](https://www.youtube.com/watch?v=uiKKRPZbuXA) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-flipflop-diagram-equation - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Show logic diagram, excitation table and characteristic equation of SR flip-flop. ## Short answer The SR flip-flop consists of NAND gates with clock gating. Excitation table: Q_n to Q_{n+1} transitions define S and R (0→0: S=0,R=X; 0→1: S=1,R=0; 1→0: S=0,R=1; 1→1: S=X,R=0). Characteristic equation: Q_{n+1} = S + R' Q_n, with the constraint SR=0. ## Answer #### Logic diagram (clocked SR flip-flop, NAND) ```text S ---[NAND1]--S'-->[NAND3]---> Q CLK -[ ] Q'-->[ ] CLK -[NAND2]--R'-->[NAND4]---> Q' R ---[ ] Q--->[ ] (Q fed to NAND4, Q' fed to NAND3) ``` NAND1 and NAND2 are steering gates enabled by CLK; NAND3 and NAND4 are cross-coupled (each output feeds the other's input). When CLK = 1: $S = 1$ sets Q to 1, $R = 1$ resets Q to 0, $S = R = 0$ holds, and $S = R = 1$ is not allowed. #### Excitation table | $Q_n$ | $Q_{n+1}$ | S | R | |---|---|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | X | 0 | #### Characteristic equation From the characteristic table ($S = R = 1$ taken as don't care): | S | R | $Q_n$ | $Q_{n+1}$ | |---|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | X | X | ```text RQn=00 01 11 10 S=0 0 1 0 0 S=1 1 1 X X ``` - The $S = 1$ row (with X) gives $S$; cells 001, 101 give $R'Q_n$. $$ Q_{n+1} = S + R'\,Q_n, \qquad \text{with } SR = 0 $$ ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What are the roles of the NAND gates in the clocked SR flip-flop? A. Two NANDs are inverters B. All four form one cross-coupled latch C. NAND3 and NAND4 are steering; NAND1 and NAND2 store D. NAND1 and NAND2 are steering gates enabled by CLK; NAND3 and NAND4 are cross-coupled Answer: D. The input gates are enabled by CLK and the cross-coupled pair holds the state. (Key point: Circuit) 2. What S and R are needed for Qn = 0 to Qn+1 = 1? A. S = 1, R = 0 B. S = 0, R = 1 C. S = 1, R = 1 D. S = X, R = 0 Answer: A. Setting needs S = 1 and R = 0. (Key point: Excitation 0 to 1) 3. What is the characteristic equation of the SR flip-flop? A. Qn+1 = S R' + Qn B. Qn+1 = S + R' Qn, with SR = 0 C. Qn+1 = S R + Qn' D. Qn+1 = S' + R Qn Answer: B. From the K-map with S=R=1 as don't care, you get S + R'Qn. (Key point: Characteristic equation) 4. What is the condition on S and R? A. S = R = 0 is not allowed B. S = 0, R = 1 is not allowed C. S = R = 1 is not allowed D. S = 1, R = 0 is not allowed Answer: C. S = R = 1 is the forbidden state, so SR = 0 is required. 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