--- title: "SR flip-flop with tables, equation, timing" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sr-flipflop-full-description" source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-flipflop-full-description site: BCT Engineering --- # SR flip-flop with tables, equation, timing Digital Logic · Chapter 6: Flip Flops - Asked in: 2075 Chaitra, 8 marks - Video: [Truth Table, Characteristic Table and Excitation Table for SR Flip Flop](https://www.youtube.com/watch?v=uiKKRPZbuXA) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-flipflop-full-description - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Explain operation of S-R flip-flop with its logical diagram, characteristics table, characteristics equation, excitation table and timing diagram. ## Short answer An S-R flip-flop has S (set) and R (reset). S=R=0 holds; S=1,R=0 sets; S=0,R=1 resets; S=R=1 is invalid. Equation: Q+ = S + R'·Q (SR=0). Excitation: 0→0 S=0,R=x; 0→1 S=1,R=0; 1→0 S=0,R=1; 1→1 S=x,R=0. ## Answer An **S-R (Set-Reset) flip-flop** is a clocked bistable circuit with inputs S and R. When the clock is active, S = 1 sets Q to 1 and R = 1 resets Q to 0; S = R = 0 keeps the old state; S = R = 1 is not allowed. #### Logic diagram (clocked S-R using NAND gates) ```text +------+ S* +------+ S -------| NAND |----->| NAND |-----> Q CLK --+--| G1 | Q'->| G3 | | +------+ +------+ | +------+ R* +------+ +--| NAND |----->| NAND |-----> Q' R -------| G2 | Q-->| G4 | +------+ +------+ G3 and G4 form a cross-coupled NAND latch. ``` ```text +---------+ S ---| S Q |--- Q CLK -|> | R ---| R Q' |--- Q' +---------+ ``` #### Operation G1 and G2 are steering gates; G3-G4 is an active-low NAND latch. (If CLK is replaced by the narrow pulse from an edge detector, this becomes the edge-triggered flip-flop shown by the symbol and used in the timing diagram below.) 1. **CLK = 0:** G1 = G2 = 1, the latch holds: no change whatever S and R are. 2. **CLK = 1, S = 0, R = 0:** G1 = G2 = 1, no change. 3. **CLK = 1, S = 1, R = 0:** G1 = 0 makes G3 output 1: Q = 1 (set). 4. **CLK = 1, S = 0, R = 1:** G2 = 0 makes G4 output 1: Q' = 1, Q = 0 (reset). 5. **CLK = 1, S = R = 1:** G1 = G2 = 0, both Q and Q' become 1: invalid. When the clock goes low, the final state is unpredictable. #### Characteristic table | S | R | Q (present) | Q+ (next) | Action | |---|---|---|---|---| | 0 | 0 | 0 | 0 | No change | | 0 | 0 | 1 | 1 | No change | | 0 | 1 | 0 | 0 | Reset | | 0 | 1 | 1 | 0 | Reset | | 1 | 0 | 0 | 1 | Set | | 1 | 0 | 1 | 1 | Set | | 1 | 1 | 0 | ? | Invalid | | 1 | 1 | 1 | ? | Invalid | #### Characteristic equation ```text K-map for Q+ (rows Q, columns SR) Q\SR 00 01 11 10 0 0 0 x 1 1 1 0 x 1 Groups: S (columns 11,10) R'.Q (row 1, columns 00,10) ``` $$ Q_{n+1} = S + \overline{R}\,Q_n, \qquad \text{with } S \cdot R = 0 $$ #### Excitation table | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | - 0 to 0: S = 0 (R may be 0 or 1). - 0 to 1: set, S = 1, R = 0. - 1 to 0: reset, S = 0, R = 1. - 1 to 1: R = 0 (S may be 0 or 1). #### Timing diagram (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾| S ‾‾‾|___________|‾‾‾|____ R _______|‾‾‾|_______|‾‾‾| Q _|‾‾‾‾‾‾‾|_______|‾‾‾|__ ``` Q goes to 1 at the edge where S = 1, to 0 at the edge where R = 1, and does not change where S = R = 0. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. With CLK = 1, S = 0 and R = 1, what does the S-R flip-flop do? A. Sets Q = 1 B. Resets Q = 0 C. Holds the state D. Becomes invalid Answer: B. G2 output goes 0, which makes Q' = 1 and Q = 0 (reset). (Key point: Set and reset operation) 2. With CLK = 1 and S = R = 1, what happens? A. Q toggles B. Both Q and Q' become 1, which is invalid and unpredictable when the clock falls C. The flip-flop resets D. The flip-flop sets Answer: B. G1 = G2 = 0 forces both latch outputs to 1. (Key point: Invalid input) 3. What is the characteristic equation of the S-R flip-flop? A. Q+ = S + R'Q with S.R = 0 B. Q+ = S'R + Q C. Q+ = SR + Q' D. Q+ = S R' Answer: A. From the K-map, Q+ = S + R'Q, with the condition S.R = 0. (Key point: Characteristic equation) 4. For the change Q = 1 to Q+ = 1, what S and R are needed? A. S = 1, R = 0 only B. S = x, R = 0 C. S = 0, R = 1 D. S = x, R = 1 Answer: B. R must be 0 (no reset), and S may be 0 or 1. (Key point: Excitation table) ## Close variants set in other exams - [JK flip-flop with tables and timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-timing-diagram) — Digital Logic, chapter 6, asked 2× ## Related in Digital Logic - [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6 - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [SR drawbacks; D flip-flop operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-d-flipflop) — Digital Logic, chapter 6 - [D flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ad-flipflop-excitation) — Digital Logic, chapter 6 - [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6 - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 ## Related in other subjects - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2