--- title: "SR to JK flip-flop conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sr-to-jk-conversion" source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-to-jk-conversion site: BCT Engineering --- # SR to JK flip-flop conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2081 Baisakh, 6 marks; 2079 Bhadra, 6 marks (asked 2 times) - Video: [SR Flip Flop to JK Flip Flop Conversion](https://www.youtube.com/watch?v=NytpDrESCV8) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-to-jk-conversion - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question With the help of RS flip-flop, realize JK flip-flop using excitation table and required expressions. ## Short answer Combinational logic drives S and R of an SR flip-flop from J, K, Qn. Excitation table yields S = J·Qn', R = K·Qn. This prevents SR=11 and implements JK behavior: set when J=1, reset when K=1, hold when both 0, toggle when both 1. ## Answer To make a JK flip-flop from an SR flip-flop, the JK inputs and the present state $Q_n$ are fed to a small combinational circuit whose outputs drive S and R. The circuit is found from the JK characteristic table and the SR excitation table. #### SR excitation table | $Q_n$ | $Q_{n+1}$ | S | R | |---|---|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | X | 0 | #### Conversion table | J | K | $Q_n$ | $Q_{n+1}$ | S | R | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | X | | 0 | 0 | 1 | 1 | X | 0 | | 0 | 1 | 0 | 0 | 0 | X | | 0 | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | X | 0 | | 1 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | 1 | #### K-maps ```text S: KQn=00 01 11 10 R: KQn=00 01 11 10 J=0 0 X 0 0 J=0 X 0 1 X J=1 1 X 0 1 J=1 0 0 1 0 ``` - S: the two 1s at ($J=1$, $Q_n=0$), cells 100 and 110, form a pair giving $S = JQ_n'$ (the X cells are not needed). - R: the 1s at ($K=1$, $Q_n=1$), cells 011 and 111, form a pair giving $R = KQ_n$. $$ S = J\,Q_n', \qquad R = K\,Q_n $$ #### Circuit ```text J ---[AND]----- S +---------+ Q'---[ ] | SR FF |--+-- Q | CLK | | K ---[AND]----- R | |--|-+-- Q' Q ---[ ] +---------+ | | (Q and Q' fed back to the AND gates) ``` Check: $J = K = 1$: if $Q_n = 0$, $S = 1, R = 0$ so $Q$ sets to 1; if $Q_n = 1$, $S = 0, R = 1$ so $Q$ resets. The output toggles, and the forbidden $S = R = 1$ never occurs, because $S$ and $R$ need opposite values of $Q_n$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. To realize a JK flip-flop from an SR flip-flop, what is needed? A. A combinational circuit with inputs J, K, Qn driving S and R, found from the JK table and SR excitation table B. Two SR flip-flops in series with no extra gates C. A counter on the clock D. Only an inverter between J and K Answer: A. The conversion table lists the S and R values needed for each JK transition, and K-maps give the logic. (Key point: Method) 2. What are the simplified expressions for S and R? A. S = J K', R = K J' B. S = J Qn', R = K Qn C. S = J + Qn, R = K + Qn' D. S = J Qn, R = K Qn' Answer: B. S must be 1 only when J=1 and Qn=0; R must be 1 only when K=1 and Qn=1. (Key point: Result) 3. For the transition Qn = 1 to Qn+1 = 1, what S and R does the SR excitation table require? A. S = 0, R = X B. S = 1, R = 0 C. S = X, R = 0 D. S = 0, R = 1 Answer: C. To stay at 1, R must be 0, and S may be 0 (hold) or 1 (set), so S is a don't care. (Key point: Excitation use) 4. Why does S = R = 1 never occur in this circuit? A. J and K cannot both be 1 B. The clock prevents it C. The SR flip-flop ignores it D. S needs Qn = 0 and R needs Qn = 1, so they cannot both be 1 Answer: D. S = JQn' and R = KQn use opposite values of Qn, so both are never 1 together; J = K = 1 toggles. (Key point: Toggle and invalid state) ## Related in Digital Logic - [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6 - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [JK to SR flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-to-sr-conversion) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6 ## Related in other subjects - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9