--- title: "SR to T conversion and SR timing diagram" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sr-to-t-conversion" source: https://www.bctengineer.com/q/semester_3/digital_logic/sr-to-t-conversion site: BCT Engineering --- # SR to T conversion and SR timing diagram Digital Logic · Chapter 6: Flip Flops - Asked in: 2078 Bhadra, 4+2 marks - Video: [SR Flip Flop to T Flip Flop Conversion](https://www.youtube.com/watch?v=B9eUdgCKEkg) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sr-to-t-conversion - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Convert SR flip-flop to T flip-flop and draw the timing diagram of SR flip flop. ## Short answer Derive S = T·Q' and R = T·Q from the SR excitation table. Connect T AND Q' to S, and T AND Q to R of an SR flip-flop. For T=0, S=R=0 holds state; for T=1, the output toggles with no invalid S=R=1. A timing diagram shows set on S=1 edge, reset on R=1 edge. ## Answer #### Converting S-R flip-flop to T flip-flop A T flip-flop must hold for T = 0 and toggle for T = 1. We generate S and R from T and Q. S-R excitation table: | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | Conversion table (Q+ = T XOR Q, then S and R from the excitation table): | T | Q | Q+ | S | R | |---|---|---|---|---| | 0 | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | 0 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | K-maps: ```text K-map for S Q\T 0 1 0 0 1 1 x 0 K-map for R Q\T 0 1 0 x 0 1 0 1 ``` $$ S = T\,\overline{Q}, \qquad R = T\,Q $$ ```text +-----+ +---------+ T --+----->| | | | | Q' ->| AND |----->| S Q |---> Q | +-----+ | | | +-----+ CLK->|> SR | +----->| | | | Q -->| AND |----->| R Q' |---> Q' +-----+ +---------+ (Q and Q' are fed back from the outputs) ``` Check: T = 1, Q = 0 gives S = 1, R = 0 (Q goes to 1); T = 1, Q = 1 gives S = 0, R = 1 (Q goes to 0); T = 0 gives S = R = 0 (hold). S and R are never 1 together. #### Timing diagram of S-R flip-flop (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾| S ‾‾‾|___________|‾‾‾|____ R _______|‾‾‾|_______|‾‾‾| Q _|‾‾‾‾‾‾‾|_______|‾‾‾|__ ``` S = 1 sets Q at an edge, R = 1 resets it, S = R = 0 keeps the old value. S = R = 1 is not applied because it is invalid. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What must the converted T flip-flop do? A. Set for T = 1 B. Hold for T = 0 and toggle for T = 1 C. Reset for T = 0 D. Toggle for T = 0 Answer: B. Q+ = T xor Q: hold for 0, toggle for 1. (Key point: T requirement) 2. What are the S and R inputs for the S-R to T conversion? A. S = T Q, R = T Q' B. S = T + Q', R = T + Q C. S = T Q', R = T Q D. S = T, R = T' Answer: C. K-maps give S = T Q' and R = T Q. (Key point: Result) 3. With T = 1 and Q = 1, what are S and R? A. S = 1, R = 0 B. S = 0, R = 1, so Q goes to 0 C. S = 1, R = 1 D. S = 0, R = 0 Answer: B. S = T Q' = 0 and R = T Q = 1, so the flip-flop resets (toggles to 0). (Key point: Toggle check) 4. In the S-R timing diagram, when does Q go to 0? A. At the edge where S = 1 B. At the edge where R = 1 C. At every edge D. When S = R = 0 Answer: B. R = 1 at an active edge resets Q; S = R = 0 keeps the old value. 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