---
title: "Machine from 4-state diagram using SR"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:state-diagram-four-state-sr"
source: https://www.bctengineer.com/q/semester_3/digital_logic/state-diagram-four-state-sr
site: BCT Engineering
---

# Machine from 4-state diagram using SR

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2081 Baisakh, 10 marks
- Video: [Design of Clocked Sequential Circuit | for given State Diagram | using JK Flip flops](https://www.youtube.com/watch?v=zxThLeS2sk8) — Learn with Dr. Shobha Nikam
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/state-diagram-four-state-sr
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a synchronous sequential machine from the given state diagram. Use SR flip-flops for realization. [Figure: state diagram with four states 00, 01, 10, 11, edges labelled input/output: 00→00 on 1/1; 00→01 on 0/0; 01→01 on 0/1; 01→10 on 1/0; 10→10 on 1/0; 10→11 on 0/0; 11→11 on 0/1; 11→00 on 1/0]

## Short answer

States are directly coded 00, 01, 10, 11. SR flip-flop equations: S1 = Q1' Q0 X, R1 = Q1 Q0 X, S0 = X', R0 = X; output Z = Q0 X' + Q1' Q0' X.

## Answer

The diagram is a Mealy machine with 4 states already coded as $Q_1 Q_0$ = 00, 01, 10, 11, so no extra state assignment is needed. Input X, output Z, two **S-R** flip-flops ($Q_1$ = MSB). Each state stays in itself on one input value and moves to the next state on the other.

#### State diagram (given)

```text
Arc label = input/output

 00 --0/0--> 01 --1/0--> 10 --0/0--> 11 --1/0--> 00

 00 --1/1--> 00  (self loop)
 01 --0/1--> 01  (self loop)
 10 --1/0--> 10  (self loop)
 11 --0/1--> 11  (self loop)
```

#### State table

| Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) |
|---|---|---|---|---|
| 00 | 01 | 00 | 0 | 1 |
| 01 | 01 | 10 | 1 | 0 |
| 10 | 11 | 10 | 0 | 0 |
| 11 | 11 | 00 | 1 | 0 |

#### Excitation table of S-R flip-flop

| Q | Q+ | S | R |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | x | 0 |

#### Transition and excitation table

| Q1 Q0 | X | Q1+ Q0+ | S1 | R1 | S0 | R0 | Z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 1 | 0 | x | 1 | 0 | 0 |
| 0 0 | 1 | 0 0 | 0 | x | 0 | x | 1 |
| 0 1 | 0 | 0 1 | 0 | x | x | 0 | 1 |
| 0 1 | 1 | 1 0 | 1 | 0 | 0 | 1 | 0 |
| 1 0 | 0 | 1 1 | x | 0 | 1 | 0 | 0 |
| 1 0 | 1 | 1 0 | x | 0 | 0 | x | 0 |
| 1 1 | 0 | 1 1 | x | 0 | x | 0 | 1 |
| 1 1 | 1 | 0 0 | 0 | 1 | 0 | 1 | 0 |

#### K-maps and simplified equations

```text
S1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    1
Q1Q0=11       x    0
Q1Q0=10       x    x

R1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       x    0
Q1Q0=11       0    1
Q1Q0=10       0    0

S0          X=0  X=1
Q1Q0=00       1    0
Q1Q0=01       x    0
Q1Q0=11       x    0
Q1Q0=10       1    0

R0          X=0  X=1
Q1Q0=00       0    x
Q1Q0=01       0    1
Q1Q0=11       0    1
Q1Q0=10       0    x

Z           X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       1    0
Q1Q0=11       1    0
Q1Q0=10       0    0
```

$$
\begin{aligned} S_1 &= Q_1' Q_0 X \\ R_1 &= Q_1 Q_0 X \\ S_0 &= X' \\ R_0 &= X \\ Z &= Q_0 X' + Q_1' Q_0' X \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+
```

Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

- $S_1$: a 3-input AND for $Q_1' Q_0 X$.
- $R_1$: a 3-input AND for $Q_1 Q_0 X$.
- $S_0$: direct line $X'$.
- $R_0$: direct line $X$.
- $Z$: a 2-input AND for $Q_0 X'$; a 3-input AND for $Q_1' Q_0' X$, combined in a 2-input OR gate.

**Check:** from 00, X = 10101 gives states 00 → 00 → 01 → 10 → 11 → 00 and Z = 10000, matching the diagram. $S_1 R_1$ and $S_0 R_0$ are never both 1.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is no separate state assignment step needed?
   A. The diagram's states are already coded 00, 01, 10, 11
   B. S-R flip-flops need none
   C. Only one state is used
   D. The output is the state
   Answer: A. The given diagram labels the states with their codes Q1Q0. (Key point: State assignment)

2. In state 11 with X=1 (next state 00), what are S1, R1?
   A. S1 = 1, R1 = 0
   B. S1 = 0, R1 = 1
   C. S1 = x, R1 = 0
   D. S1 = 0, R1 = 0
   Answer: B. Both flip-flops go from 1 to 0, so S = 0 and R = 1. (Key point: Flip-flop going 1 to 0)

3. Which output equation was found?
   A. Z = Q1 X
   B. Z = Q0 X + Q1 X'
   C. Z = Q0 X' + Q1' Q0' X
   D. Z = Q1' Q0 X
   Answer: C. Z = 1 for states 01 and 11 on X=0 and for 00 on X=1. (Key point: Output)

4. Which S-R input combination must never occur?
   A. S = 0, R = 0
   B. S = 1, R = 0
   C. S = x, R = 0
   D. S = 1, R = 1
   Answer: D. S = R = 1 is invalid for an S-R flip-flop; the answer checks it never happens. (Key point: S-R rule)

## Related in Digital Logic

- [Machine from 3-state diagram using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Astate-diagram-xyz-sr) — Digital Logic, chapter 9
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-sr-msb) — Digital Logic, chapter 9
- [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8
- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-t) — Digital Logic, chapter 9

## Related in other subjects

- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
