---
title: "Machine from 3-state diagram using SR"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:state-diagram-xyz-sr"
source: https://www.bctengineer.com/q/semester_3/digital_logic/state-diagram-xyz-sr
site: BCT Engineering
---

# Machine from 3-state diagram using SR

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2075 Asoj, 10 marks
- Video: [Design of Clocked Sequential Circuit | for given State Diagram | using JK Flip flops](https://www.youtube.com/watch?v=zxThLeS2sk8) — Learn with Dr. Shobha Nikam
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/state-diagram-xyz-sr
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a synchronous sequential machine from the state diagram given below. Use S-R Flip-Flop. [Figure: state diagram with three states X, Y, Z, edges labelled input/output: X→X on 0/0; X→Y on 1/0; Y→X on 0/0; Y→Z on 1/0; Z→Z on 1/1; Z→X on 0/0]

## Short answer

Assign states X=00, Y=01, Z=10. Output F=1 only in Z with W=1 (three consecutive 1s). S1=Q0 W, R1=W', S0=Q1' Q0' W, R0=Q0, F=Q1 W. Two S-R flip-flops.

## Answer

The state diagram is a Mealy diagram with 3 states. To avoid confusion with the state names X, Y, Z, the input is called **W** and the output **F**. From the diagram, F = 1 only when the machine is in Z and W = 1, i.e. the machine detects three or more consecutive 1s. Flip-flops: **S-R**.

#### State diagram (given)

```text
Arc label = input/output

 X --1/0--> Y --1/0--> Z --1/1--> Z

 X --0/0--> X  (self loop)
 Y --0/0--> X
 Z --0/0--> X
```

#### State table

| Present state | Next, W=0 | Next, W=1 | F (W=0) | F (W=1) |
|---|---|---|---|---|
| X | X | Y | 0 | 0 |
| Y | X | Z | 0 | 0 |
| Z | X | Z | 0 | 1 |

#### State assignment

X = 00, Y = 01, Z = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (W=0 goes to X, W=1 goes to Z), so it is self-starting.

#### Excitation table of S-R flip-flop

| Q | Q+ | S | R |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | x | 0 |

#### Transition and excitation table

| Q1 Q0 | W | Q1+ Q0+ | S1 | R1 | S0 | R0 | F |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | x | 0 | x | 0 |
| 0 0 | 1 | 0 1 | 0 | x | 1 | 0 | 0 |
| 0 1 | 0 | 0 0 | 0 | x | 0 | 1 | 0 |
| 0 1 | 1 | 1 0 | 1 | 0 | 0 | 1 | 0 |
| 1 0 | 0 | 0 0 | 0 | 1 | 0 | x | 0 |
| 1 0 | 1 | 1 0 | x | 0 | 0 | x | 1 |

#### K-maps and simplified equations

```text
S1          W=0  W=1
Q1Q0=00       0    0
Q1Q0=01       0    1
Q1Q0=11       x    x
Q1Q0=10       0    x

R1          W=0  W=1
Q1Q0=00       x    x
Q1Q0=01       x    0
Q1Q0=11       x    x
Q1Q0=10       1    0

S0          W=0  W=1
Q1Q0=00       0    1
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       0    0

R0          W=0  W=1
Q1Q0=00       x    0
Q1Q0=01       1    1
Q1Q0=11       x    x
Q1Q0=10       x    x

F           W=0  W=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       0    1
```

$$
\begin{aligned} S_1 &= Q_0 W \\ R_1 &= W' \\ S_0 &= Q_1' Q_0' W \\ R_0 &= Q_0 \\ F &= Q_1 W \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 W  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> F
 W  ------>| logic       |
           +-------------+
```

Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

- $S_1$: a 2-input AND for $Q_0 W$.
- $R_1$: direct line $W'$.
- $S_0$: a 3-input AND for $Q_1' Q_0' W$.
- $R_0$: direct line $Q_0$.
- $F$: a 2-input AND for $Q_1 W$.

**Check:** input W = 0111101 gives F = 0001100 — F = 1 at the 3rd and 4th consecutive 1, as the diagram requires (Z → Z on 1/1).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does this state diagram detect?
   A. The sequence 011 only
   B. Three or more consecutive 1s (output 1 on each 1 after the second)
   C. Exactly two 1s
   D. The sequence 101
   Answer: B. Z loops on itself with W = 1 and gives F = 1, so every 1 after two consecutive 1s outputs 1. (Key point: What the machine does)

2. Why is F = Q1 W?
   A. F is 1 in state Y (01) with W = 0
   B. F is 1 in state X with W = 1
   C. F is 1 only in state Z (10) with W = 1, and 11 is a don't care
   D. F is 1 for every W = 1
   Answer: C. Only the arc Z to Z on 1/1 has an output of 1, and Q1 = 1 only in state Z. (Key point: Output equation)

3. For a 1 to 1 transition in an S-R flip-flop, what are S and R?
   A. S = 0, R = 1
   B. S = 1, R = 0
   C. S = 1, R = 1
   D. S = x, R = 0
   Answer: D. To hold a 1, R must be 0 and S may be anything (0 or 1), so S = x. (Key point: S-R excitation)

4. What happens from the unused code 11?
   A. The machine locks up
   B. It goes to a valid state on the next clock (X on W=0, Z on W=1), so it is self-starting
   C. It goes to state Y
   D. F stays 1 forever
   Answer: B. Checking the final equations shows 11 moves to X when W = 0 and to Z when W = 1. (Key point: Unused state)

## Related in Digital Logic

- [Machine from 4-state diagram using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Astate-diagram-four-state-sr) — Digital Logic, chapter 9
- [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6
- [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6
- [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×
- [SR drawbacks; D flip-flop operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-d-flipflop) — Digital Logic, chapter 6

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- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
