---
title: "Static and dynamic hazards and their elimination"
subject: "Digital Logic"
chapter: 3
key: "semester_3/digital_logic:static-dynamic-hazards"
source: https://www.bctengineer.com/q/semester_3/digital_logic/static-dynamic-hazards
site: BCT Engineering
---

# Static and dynamic hazards and their elimination

Digital Logic · Chapter 3: Combinational Logic Circuits

- Asked in: 2074 Chaitra, 4+2 marks; 2074 Asoj, 3 marks (asked 2 times)
- Video: [U4L6 | Hazard | static & dynamic hazard | hazard free circuit in digital electronics | ques 6(b)](https://www.youtube.com/watch?v=lm-6lom3pqw) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/static-dynamic-hazards
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3

## Question

What do you mean by static and dynamic hazards? Give example of static hazards and explain how do you eliminate such hazards?

## Short answer

Static hazard: output momentarily changes when it should stay constant (e.g., static-1: 1→0→1). Dynamic hazard: output changes multiple times during a transition. Example: F = AB + A'C with B=C=1 causes a static-1 glitch. Eliminate by adding consensus term BC to cover adjacent 1s in the K-map.

## Answer

A **hazard** is an unwanted short pulse (glitch) at the output of a combinational circuit. It happens when an input changes and different signal paths have different propagation delays, so the output briefly takes a wrong value even though the steady-state value is correct.

#### Static hazard

The output should stay at the same value, but it momentarily changes and comes back.

- **Static-1 hazard:** output should stay 1 but goes $1 \to 0 \to 1$. Occurs in SOP (AND-OR) circuits.
- **Static-0 hazard:** output should stay 0 but goes $0 \to 1 \to 0$. Occurs in POS (OR-AND) circuits.

#### Dynamic hazard

The output should change once ($0 \to 1$ or $1 \to 0$) but it changes three or more times, e.g. $0 \to 1 \to 0 \to 1$. It happens in multi-level circuits where one input reaches the output through three or more paths of different delay. A circuit that is free of static hazards at every level (a two-level hazard-free design) is also free of dynamic hazards.

#### Example of a static-1 hazard

$$
F = AB + \overline{A}C
$$

Let $B = C = 1$. Then $F = A + \overline{A} = 1$ for both values of A, so F should stay at 1.

```text
A ──┬──────────[AND]── AB ──┐
    │     B ───┘            [OR]── F
    └─[NOT]──A'─[AND]─ A'C ─┘
          C ────┘
```

When A falls from 1 to 0, AB goes to 0 at once, but A'C rises only after the inverter delay. For that short time both AND outputs are 0, so F dips to 0: a static-1 hazard.

```text
A    ‾‾‾‾‾|_________
AB   ‾‾‾‾‾|_________
A'C  ______|‾‾‾‾‾‾‾‾   (late by inverter delay)
F    ‾‾‾‾‾|_|‾‾‾‾‾‾‾   (glitch)
```

#### Eliminating the hazard

On the K-map, the two groups AB (cells 6, 7) and A'C (cells 1, 3) sit next to each other (cells 3 and 7) but no group covers both. A move between two adjacent 1-cells that are in different groups is a hazard.

The fix is to add a redundant group (the **consensus term**) that covers the adjacent cells:
$$
F = AB + \overline{A}C + BC
$$

When $B = C = 1$, the extra term $BC = 1$ holds F at 1 while A changes, so the glitch is removed. The logic function is unchanged because $BC$ is the consensus of $AB$ and $\overline{A}C$.

Rule: in an SOP circuit, make sure every pair of adjacent 1s on the K-map is covered by at least one common group. For POS circuits, do the same with the 0s to remove static-0 hazards.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. A hazard arises because:
   A. Signal paths have different propagation delays
   B. Supply voltage drops
   C. The truth table is wrong
   D. Gates are NAND
   Answer: A. Different delays cause glitches. (Key point: Hazard cause)

2. Static-1 hazard:
   A. Output should stay 0 but spikes to 1
   B. Output should stay 1 but dips to 0
   C. Output changes 3 times
   D. Output stuck
   Answer: B. It occurs in SOP circuits. (Key point: Static-1)

3. Dynamic hazard:
   A. Output glitches while static
   B. Never happens
   C. Output changes three or more times instead of once
   D. Output changes once
   Answer: C. E.g. 0-1-0-1. (Key point: Dynamic)

4. Fix for F = AB + A'C:
   A. Remove A'C
   B. Add ABC
   C. Use a slower inverter
   D. Add consensus term BC
   Answer: D. BC holds F at 1 while A changes. (Key point: Fix)

## Related in Digital Logic

- [Switch bounce; negative edge RS flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aswitch-bounce-negative-edge-rs) — Digital Logic, chapter 6

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