--- title: "Switch bounce; negative edge RS flip-flop" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:switch-bounce-negative-edge-rs" source: https://www.bctengineer.com/q/semester_3/digital_logic/switch-bounce-negative-edge-rs site: BCT Engineering --- # Switch bounce; negative edge RS flip-flop Digital Logic · Chapter 6: Flip Flops - Asked in: 2079 Bhadra, 3+5 marks - Video: [Edge Triggered SR Flip Flop or Clocked SR Flip Flop](https://www.youtube.com/watch?v=JnkNkBsn_Oo) — Engg-Course-Made-Easy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/switch-bounce-negative-edge-rs - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question How do you eliminate the switch contacts bounce circuits? Explain the operation of negative edge triggered RS flip-flop along with excitation table. ## Short answer Switch bounce is eliminated by an SR latch debouncer: an SPDT switch makes first contact set/reset the latch, and bounces cause S'=R'=1, holding the state. A negative edge-triggered RS flip-flop updates only at the falling clock edge. Excitation table: Q_n to Q_{n+1} gives S,R: 0→0: 0,X; 0→1: 1,0; 1→0: 0,1; 1→1: X,0. ## Answer #### Eliminating switch contact bounce When a mechanical switch is closed or opened, its contacts bounce several times for a few milliseconds, so a digital circuit sees many pulses instead of one clean transition. **Method 1: SR (NAND) latch debouncer** using an SPDT switch: ```text +5V-[R1]-+-------S'-->+--------+ | | NAND |--> Q (clean) A o-+ | SR | \ | latch |--> Q' GND --o (arm) | | B o-+ | | | | | +5V-[R2]-+-------R'-->+--------+ ``` - When the switch moves from A to B, the first touch at B resets the latch. - Bounces at B only make R' go 1, 0, 1, ...; with S' = 1 and R' = 1 the latch **holds** its state, so the output stays clean. - The output changes only once, at the first contact. **Method 2:** an RC filter followed by a Schmitt-trigger inverter (e.g. 74HC14); the capacitor smooths the bounces and the hysteresis gives one clean edge. **Method 3:** software delay (about 10–20 ms) in microcontrollers. #### Negative edge-triggered RS flip-flop It changes state only at the **falling edge** of the clock. An edge detector makes a very narrow pulse CLK* when CLK goes from 1 to 0, and the steering gates G1 and G2 are enabled only during this pulse. Symbol: triangle with a bubble at CLK. ```text CLK --+--->[ NOT ]----------->+-----+ | | AND |---> CLK* +--->[ delay dt ]------>+-----+ CLK* = CLK' . CLK(delayed): a narrow pulse at every falling edge of CLK ``` ```text +------+ S* +------+ S -------| NAND |----->| NAND |-----> Q CLK* ----| G1 | Q'->| G3 | +------+ +------+ +------+ R* +------+ R -------| NAND |----->| NAND |-----> Q' CLK* ----| G2 | Q-->| G4 | +------+ +------+ G3 and G4 form a cross-coupled NAND latch. ``` | CLK | S | R | $Q_{n+1}$ | |---|---|---|---| | Falling edge | 0 | 0 | $Q_n$ (hold) | | Falling edge | 0 | 1 | 0 (reset) | | Falling edge | 1 | 0 | 1 (set) | | Falling edge | 1 | 1 | Invalid | | 0, 1, rising | X | X | $Q_n$ | **Excitation table** | $Q_n$ | $Q_{n+1}$ | S | R | |---|---|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | X | 0 | Characteristic equation: $Q_{n+1} = S + R'Q_n$ with $SR = 0$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is switch contact bounce? A. A permanent short B. Noise from the clock C. A slow rise time of the supply D. The contacts bounce for a few milliseconds when thrown, so the circuit sees many pulses instead of one clean transition Answer: D. Mechanical contacts vibrate for a few ms and cause multiple transitions. (Key point: Contact bounce) 2. Why does an SR (NAND) latch with an SPDT switch give a clean output? A. Bounces at B only give S' = R' = 1 (hold) between touches, so the output changes once at the first contact B. The latch filters out the high frequencies C. The latch resets at every bounce to a new value D. It adds an RC delay Answer: A. The first touch resets the latch; bounces leave both inputs high, which holds the state. (Key point: Latch debouncer) 3. Which is another method of removing bounce? A. A full adder B. An RC filter followed by a Schmitt-trigger inverter C. A larger pull-up on the clock D. A decoder Answer: B. The capacitor smooths bounces and the hysteresis gives one clean edge. (Key point: Other methods) 4. What happens at the falling edge of a negative edge-triggered RS flip-flop with S = 1, R = 0? A. Hold B. Reset C. Set D. Invalid Answer: C. S=1,R=0 sets Q; the flip-flop changes only at the falling edge. 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