--- title: "Synchronous vs asynchronous circuits; SR to JK" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:sync-async-sr-to-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/sync-async-sr-to-jk site: BCT Engineering --- # Synchronous vs asynchronous circuits; SR to JK Digital Logic · Chapter 6: Flip Flops - Asked in: 2082 Shrawan, 2+6 marks - Video: [Asynchronous & Synchronous Sequential Circuit |KVS Computer Science|L-31|Digital Electronics|Part-11](https://www.youtube.com/watch?v=YDsE3ueCZNA) — Easy Learning 247 - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sync-async-sr-to-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Differentiate between synchronous and asynchronous sequential logic circuits. How to convert SR flip-flop into JK flip-flop? ## Short answer Synchronous circuits change state only at clock edges using a common clock; asynchronous circuits respond immediately to input changes without a clock and suffer from race conditions. Convert SR to JK by deriving S = J Q' and R = K Q from excitation and K-map; implement with AND gates feeding the SR’s S and R inputs. ## Answer #### Synchronous vs asynchronous sequential circuits | Point | Synchronous sequential | Asynchronous sequential | |---|---|---| | State change | Only at clock edges | Whenever inputs change | | Clock | Common clock needed | No clock (or not common) | | Memory elements | Clocked flip-flops | Latches / delay elements | | Speed | Limited by clock rate | Faster | | Design | Easier, reliable | Harder; races and hazards | | Example | Synchronous counter | Ripple counter, SR latch | #### Converting S-R flip-flop into J-K flip-flop **Step 1: excitation table of the available S-R flip-flop** | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | **Step 2: conversion table.** For each J, K and present state Q, find Q+ from the J-K characteristic table, then write the S and R needed for that change: | J | K | Q | Q+ | S | R | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | x | | 0 | 0 | 1 | 1 | x | 0 | | 0 | 1 | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | x | 0 | | 1 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | 1 | **Step 3: K-maps** ```text K-map for S Q\JK 00 01 11 10 0 0 0 1 1 1 x 0 0 x K-map for R Q\JK 00 01 11 10 0 x x 0 0 1 0 1 1 0 ``` - S: the 1s are at Q = 0, JK = 11 and 10; the don't-cares at Q = 1 cannot enlarge this group (Q = 1, JK = 11 is 0), so $S = J\overline{Q}$. - R: the 1s are at Q = 1, JK = 01 and 11, so $R = KQ$. $$ S = J\,\overline{Q}, \qquad R = K\,Q $$ **Step 4: circuit** ```text +-----+ +---------+ J -------->| | | | Q' ------->| AND |----->| S Q |---> Q +-----+ | | +-----+ CLK->|> SR | K -------->| | | | Q ------->| AND |----->| R Q' |---> Q' +-----+ +---------+ (Q and Q' are fed back from the outputs) ``` **Check:** J = K = 1 with Q = 0 gives S = 1, R = 0 (Q becomes 1); with Q = 1 gives S = 0, R = 1 (Q becomes 0). So the circuit toggles, and S = R = 1 can never occur because S needs Q = 0 while R needs Q = 1. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. When does a synchronous sequential circuit change state? A. Whenever any input changes B. Only at clock edges C. Only when reset D. Only at power-up Answer: B. Synchronous circuits use a common clock and change state only at clock edges; asynchronous ones change whenever inputs change. (Key point: State change timing) 2. To convert an S-R flip-flop into a J-K flip-flop, what is used to find the S and R inputs? A. Only the J-K characteristic table B. The J-K excitation table C. The conversion table: Q+ from the J-K table, then S and R from the S-R excitation table D. The T flip-flop table Answer: C. For each J, K, Q take Q+ from the J-K table, then the S and R needed from the S-R excitation table. (Key point: Conversion method) 3. What are the S and R inputs for the converted J-K flip-flop? A. S = J Q, R = K Q' B. S = J Q', R = K Q C. S = J + Q', R = K + Q D. S = J, R = K Answer: B. K-maps give S = J Q' and R = K Q. (Key point: Result) 4. Why can S = R = 1 never occur in the converted circuit? A. S needs Q = 0 while R needs Q = 1 B. Because the clock blocks it C. Because J and K are never both 1 D. Because an inverter joins S and R Answer: A. S = J Q' needs Q = 0 and R = K Q needs Q = 1, so both cannot be 1 together. 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