---
title: "Sync counter for sequence 000,001,011,111,110,100"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:sync-counter-custom-sequence"
source: https://www.bctengineer.com/q/semester_3/digital_logic/sync-counter-custom-sequence
site: BCT Engineering
---

# Sync counter for sequence 000,001,011,111,110,100

Digital Logic · Chapter 8: Counters

- Asked in: 2079 Bhadra, 3+6 marks
- Video: [Designing of Random sequence in synchronous counter](https://www.youtube.com/watch?v=20vGZAwKf3M) — Learning with RACHIT MANCHANDA
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/sync-counter-custom-sequence
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

What is an asynchronous counter? Design a synchronous counter with counting sequence: 000, 001, 011, 111, 110, 100, 000, ... using JK flip-flop.

## Short answer

Asynchronous counter: only first flip-flop gets external clock, succeeding stages clocked by preceding output, causing ripple. The 6-state synchronous counter (000,001,011,111,110,100) is a Johnson ring with 3 JK flip-flops: J2=Q1Q0, K2=Q1'; J1=Q0, K1=Q0'; J0=Q2', K0=Q2. Self-starting.

## Answer

#### Asynchronous counter
An **asynchronous (ripple) counter** is a counter in which the external clock is applied only to the first flip-flop, and every other flip-flop is clocked by the output of the preceding flip-flop. The flip-flops therefore change state one after another, not together. It is simple but slow, and it shows short false states while the change ripples through.

#### Design of the synchronous counter: 000, 001, 011, 111, 110, 100, 000 …
**Step 1:** 6 states, so 3 JK flip-flops ($Q_2Q_1Q_0$) with a common clock. Unused states: 010 and 101 (don't cares).

**Step 2: Excitation table** (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 011 | 0 | X | 1 | X | X | 0 |
| 011 | 111 | 1 | X | X | 0 | X | 0 |
| 111 | 110 | X | 0 | X | 0 | X | 1 |
| 110 | 100 | X | 0 | X | 1 | 0 | X |
| 100 | 000 | X | 1 | 0 | X | 0 | X |

**Step 3: K-maps**

| J0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | X | X | X |
| 1 | 0 | X | X | 0 |

| K0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | 0 | 0 | X |
| 1 | X | X | 1 | X |

| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | X | X | X |

| K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 0 | X |
| 1 | X | X | 0 | 1 |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | X |
| 1 | X | X | X | X |

| K2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 1 | X | 0 | 0 |

**Step 4: Equations**

The minimum groups give $J_2 = Q_1$, but then the unused states form a closed loop 010 → 101 → 010, so a counter that powers up in 010 or 101 would never enter the sequence (lock-out). Taking the 1-cell 011 alone, $J_2 = Q_1Q_0$, removes this problem at the cost of one AND gate:
$$
\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = \overline{Q_1} \\ &J_1 = Q_0,\quad K_1 = \overline{Q_0} \\ &J_0 = \overline{Q_2},\quad K_0 = Q_2 \end{aligned}
$$

**Check of unused states (with $J_2 = Q_1Q_0$)**
| Unused state | Next state |
|---|---|
| 010 | 001 (in sequence) |
| 101 | 010 → 001 |

So the counter is self-starting.

**Step 5: Circuit diagram**
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q2'   K0 = Q2
J1 = Q0    K1 = Q0'
J2 = Q1.Q0 K2 = Q1'
```
The sequence is that of a 3-bit **Johnson (twisted-ring) counter**: in the count, $Q_1$ copies $Q_0$, $Q_2$ copies $Q_1$, and $Q_0$ takes the inverted $Q_2$.

**Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____________|‾‾‾‾‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾‾
Cnt  000  001 011 111 110 100 000 001
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In an asynchronous counter, how is the clock applied?
   A. The same clock goes to every flip-flop
   B. The clock goes only to the first flip-flop; each later one is clocked by the previous output
   C. The clock goes to the last flip-flop only
   D. Each flip-flop has its own independent clock
   Answer: B. Only the first stage gets the external clock, so changes ripple stage by stage, making it slow with false states. (Key point: Asynchronous counter)

2. For the sequence 000, 001, 011, 111, 110, 100, which states are don't cares?
   A. 011 and 110
   B. 000 and 111
   C. 010 and 101
   D. 001 and 100
   Answer: C. Six states are used, so the two unused states, 010 and 101, are don't cares. (Key point: Don't-care states)

3. Why is J2 = Q1Q0 chosen instead of the smaller J2 = Q1?
   A. J2 = Q1 gives wrong values in the main sequence
   B. J2 = Q1 makes 010 and 101 form a closed loop, so the counter would lock out
   C. J2 = Q1Q0 needs fewer gates
   D. J2 = Q1 would make K2 undefined
   Answer: B. With J2 = Q1 the unused states loop 010 to 101 to 010. Using J2 = Q1Q0 breaks that loop so the counter is self-starting. (Key point: Lock-out and J2)

4. Which set gives the flip-flop inputs for FF0 and FF1?
   A. J0 = Q2, K0 = Q2', J1 = Q0', K1 = Q0
   B. J0 = Q2', K0 = Q2, J1 = Q0, K1 = Q0'
   C. J0 = 1, K0 = 1, J1 = Q0, K1 = Q0
   D. J0 = Q1, K0 = Q1', J1 = Q2, K1 = Q2'
   Answer: B. The K-maps give J0 = Q2', K0 = Q2, J1 = Q0, K1 = Q0', so each stage copies the previous one and Q2 is fed back inverted (Johnson counter). (Key point: Final equations)

## Related in Digital Logic

- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 011 using RS flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-rs) — Digital Logic, chapter 9
- [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8

## Related in other subjects

- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9
- [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9