--- title: "Comb vs seq; synchronous decade counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:sync-decade-comb-seq" source: https://www.bctengineer.com/q/semester_3/digital_logic/sync-decade-comb-seq site: BCT Engineering --- # Comb vs seq; synchronous decade counter Digital Logic · Chapter 8: Counters - Asked in: 2080 Baisakh, 2+6 marks - Video: [Comparison between Combinational and Sequential Circuits](https://www.youtube.com/watch?v=SzV4l0_1MCQ) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/sync-decade-comb-seq - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Differentiate between combinational and sequential logic circuits. Explain the operation of a synchronous decade counter with timing diagrams. ## Short answer Combinational circuits' outputs rely solely on current inputs; sequential circuits have memory. A synchronous decade counter connects all four JK flip-flops to one clock. With J0=K0=1, J1=Q3'Q0, K1=Q0, J2=K2=Q1Q0, J3=Q2Q1Q0, K3=Q0, it counts 0–9 and directly resets without ripple. ## Answer #### Combinational vs sequential logic circuits | Point | Combinational circuit | Sequential circuit | |---|---|---| | Output depends on | Present inputs only | Present inputs and past state | | Memory | No memory | Has memory (flip-flops/latches) | | Feedback | No feedback path | Feedback from output to input | | Clock | Not needed | Usually clocked | | Analysis tool | Truth table | State table / state diagram | | Examples | Adder, MUX, decoder | Flip-flop, register, counter | #### Synchronous decade counter A synchronous decade counter counts 0000 to 1001 with all four flip-flops clocked together. Gates decide when each flip-flop toggles. From the excitation table of the 0–9 sequence (states 1010–1111 as don't cares), the JK equations are: $$ \begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_0 \\ &J_2 = Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = \overline{Q_3}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned} $$ **Circuit diagram** ```text +-----+ +-----+ +-----+ +-----+ J0>|J Q|-Q0 J1>|J Q|-Q1 J2>|J Q|-Q2 J3>|J Q|-Q3 | FF0 | | FF1 | | FF2 | | FF3 | K0>|K | K1>|K | K2>|K | K3>|K | +--o--+ +--o--+ +--o--+ +--o--+ | | | | CLK---+-------------+-------------+-------------+ J0 = K0 = 1 J1 = Q3'.Q0 K1 = Q0 J2 = K2 = Q1.Q0 J3 = Q2.Q1.Q0 K3 = Q0 ``` **Operation** | Count | Q3 Q2 Q1 Q0 | Flip-flops that toggle at next clock | |---|---|---| | 0 | 0000 | FF0 | | 1 | 0001 | FF0, FF1 | | 2 | 0010 | FF0 | | 3 | 0011 | FF0, FF1, FF2 | | 4 | 0100 | FF0 | | 5 | 0101 | FF0, FF1 | | 6 | 0110 | FF0 | | 7 | 0111 | FF0, FF1, FF2, FF3 (set) | | 8 | 1000 | FF0 | | 9 | 1001 | FF0, FF3 (reset); FF1 held by $\overline{Q_3} = 0$ | - FF0 toggles on every clock ($J_0 = K_0 = 1$). - FF1 toggles when $Q_0 = 1$, but at count 9 $J_1 = \overline{Q_3}Q_0 = 0$ keeps it at 0. - FF2 toggles when $Q_1Q_0 = 1$. - FF3 sets when $Q_2Q_1Q_0 = 1$ (7 → 8) and resets when $Q_0 = 1$ while $Q_3 = 1$ (9 → 0). So after count 9 (1001) the next clock gives 0000 directly, without any false state. **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|_______ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾ Cnt 0 1 2 3 4 5 6 7 8 9 0 1 ``` All outputs change at the same falling edge, so there is no ripple delay. $Q_3$ gives $f_{clk}/10$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which pair correctly contrasts the two circuit types? A. Combinational: has memory; sequential: no memory B. Combinational: no memory, output from present inputs; sequential: memory, output from inputs and past state C. Both depend only on present inputs D. Sequential circuits never use a clock Answer: B. Sequential circuits store past state in flip-flops; combinational circuits do not. (Key point: Sequential circuit memory) 2. In the synchronous decade counter, what are J0 and K0? A. J0 = K0 = 0 B. J0 = Q1, K0 = Q1 C. J0 = K0 = Q3 D. J0 = K0 = 1 Answer: D. FF0 toggles on every clock, so J0 = K0 = 1. (Key point: Toggle conditions) 3. Why is J1 = Q3'Q0 rather than just Q0? A. To stop FF1 toggling at count 9 so the count returns to 0000 directly B. To make FF1 toggle faster C. To start FF1 at count 8 D. To avoid a ripple delay Answer: A. At 1001, Q3' = 0 keeps FF1 at 0, so the next state is 0000 rather than 1010. (Key point: Holding FF1 at count 9) 4. Why does the synchronous decade counter show no false state after 1001? A. All FFs share the clock and the gates give 0000 directly B. A NAND gate clears it asynchronously C. Q3 is fed back to the clock D. It uses fewer flip-flops Answer: A. All outputs change together at the same edge, with J/K inputs set for 1001 -> 0000, so no momentary state appears. (Key point: No false states) ## Close variants set in other exams - [Comb vs seq; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-comb-seq) — Digital Logic, chapter 8, asked 4× ## Related in Digital Logic - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× - [Synchronous decade counter with timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asynchronous-decade-counter) — Digital Logic, chapter 8, asked 2× - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3× - [Combinational vs sequential; BCD-to-decimal decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-to-decimal-decoder) — Digital Logic, chapter 4 ## Related in other subjects - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6