---
title: "Sync vs async; 3-bit synchronous down counter"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:sync-down-counter-3bit"
source: https://www.bctengineer.com/q/semester_3/digital_logic/sync-down-counter-3bit
site: BCT Engineering
---

# Sync vs async; 3-bit synchronous down counter

Digital Logic · Chapter 8: Counters

- Asked in: 2081 Baisakh, 2+6 marks
- Video: [3 Bit Synchronous Up & Down Counter: Basics, Circuit, Designing, Working, and Waveforms](https://www.youtube.com/watch?v=T-CR0lJqqbo) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/sync-down-counter-3bit
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Differentiate between synchronous and asynchronous counter. Design 3-bit synchronous down counter using JK flip-flops.

## Short answer

Synchronous counters have all flip-flops share a common clock, changing simultaneously with minimal delay; asynchronous counters ripple with accumulated propagation delays. A 3-bit synchronous down counter using JK flip-flops has J0=K0=1, J1=K1=Q0', J2=K2=Q1'Q0', and counts from 7 down to 0.

## Answer

#### Synchronous vs asynchronous counter
| Point | Synchronous counter | Asynchronous (ripple) counter |
|---|---|---|
| Clock | Common clock to all flip-flops | Only FF0 gets the clock; each next FF is clocked by the previous output |
| Change of state | All flip-flops change together | Flip-flops change one after another (ripple) |
| Delay | One FF delay + gate delay | Adds up: $n \times t_{pd}$ |
| Speed | Fast, high clock frequency | Slow, frequency falls as $n$ grows |
| Circuit | Needs extra gating logic | Simple, few or no extra gates |
| Decoding glitches | None (no false states) | Momentary false states give glitches |
| Example ICs | 74160/74163, 74190 | 7490, 7493 |

#### Design of 3-bit synchronous down counter (JK)
A 3-bit down counter counts 7, 6, 5, …, 0 and then returns to 7. Three JK flip-flops ($Q_2Q_1Q_0$) share one clock.

**Excitation table** (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 111 | 110 | X | 0 | X | 0 | X | 1 |
| 110 | 101 | X | 0 | X | 1 | 1 | X |
| 101 | 100 | X | 0 | 0 | X | X | 1 |
| 100 | 011 | X | 1 | 1 | X | 1 | X |
| 011 | 010 | 0 | X | X | 0 | X | 1 |
| 010 | 001 | 0 | X | X | 1 | 1 | X |
| 001 | 000 | 0 | X | 0 | X | X | 1 |
| 000 | 111 | 1 | X | 1 | X | 1 | X |

**K-maps**

| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | 0 | X | X |
| 1 | 1 | 0 | X | X |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 |
| 1 | X | X | X | X |

$J_0$ and $K_0$ are 1 in every row (Q0 toggles every clock), so $J_0 = K_0 = 1$. $J_1$ and $K_1$ have the same map, and so do $J_2$ and $K_2$.

**Equations**
$$
\begin{aligned} &J_2 = \overline{Q_1}\overline{Q_0},\quad K_2 = \overline{Q_1}\overline{Q_0} \\ &J_1 = \overline{Q_0},\quad K_1 = \overline{Q_0} \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}
$$

In words, a stage toggles when all lower bits are 0 (the "borrow" condition), just as an up counter stage toggles when all lower bits are 1.

**Circuit diagram**
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = K1 = Q0'
J2 = K2 = Q1'.Q0'   (one 2-input AND gate)
```

**Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    7   6   5   4   3   2   1   0
```
All outputs change together on the falling clock edge, so no ripple delay or false state appears.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does a synchronous counter differ from an asynchronous one in clocking and delay?
   A. Common clock to all FFs with one FF plus gate delay, versus a ripple clock with n x t_pd delay
   B. Ripple clock with one delay, versus a common clock with n x t_pd delay
   C. Both use a common clock but differ in gates
   D. Synchronous uses no flip-flops
   Answer: A. Synchronous counters clock all flip-flops together so delay does not accumulate; ripple counters add n x t_pd. (Key point: Clock and delay difference)

2. What is the sequence of the 3-bit down counter?
   A. 0, 1, 2, ... 7
   B. 7, 6, 5, ... 0 then back to 7
   C. 7, 5, 3, 1
   D. 0, 7, 6, ... 1
   Answer: B. A down counter decrements: 111, 110, 101, ..., 000 and then returns to 111. (Key point: Down counter sequence)

3. Which JK equations are obtained?
   A. J2 = K2 = Q1 Q0, J1 = K1 = Q0, J0 = K0 = 1
   B. J2 = K2 = Q1' Q0', J1 = K1 = Q0', J0 = K0 = 1
   C. J2 = Q1', K2 = Q0', J1 = K1 = 1
   D. J0 = K0 = 0
   Answer: B. A stage toggles when all lower bits are 0 (borrow condition), so J = K = product of complements of lower bits. (Key point: Toggle (borrow) condition)

4. Why does the synchronous down counter show no false states?
   A. Because all flip-flops change together on the common clock edge
   B. Because it uses fewer gates
   C. Because only Q0 is clocked
   D. Because it uses a slower clock
   Answer: A. Common clocking makes all outputs change together, so there is no ripple delay or false state. (Key point: Glitch-free operation)

## Related in Digital Logic

- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
- [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8
- [Sync vs async; 3-bit Gray code counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Agray-sync-counter-advantages) — Digital Logic, chapter 8
- [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3×
- [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2×
- [3-bit asynchronous up/down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-up-down-counter-3bit) — Digital Logic, chapter 8, asked 2×

## Related in other subjects

- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [Transmission channels; sync vs async](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Atransmission-modes) — Data Communication, chapter 1