---
title: "Sync vs async; 3-bit synchronous up counter (T)"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:sync-up-counter-3bit-t"
source: https://www.bctengineer.com/q/semester_3/digital_logic/sync-up-counter-3bit-t
site: BCT Engineering
---

# Sync vs async; 3-bit synchronous up counter (T)

Digital Logic · Chapter 8: Counters

- Asked in: 2080 Bhadra, 2+6 marks
- Video: [3 Bit Synchronous Counter Using T Flip-Flops: Basics, Circuit, Designing, Working, and Waveforms](https://www.youtube.com/watch?v=KcmfnPOLIdI) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/sync-up-counter-3bit-t
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Compare synchronous and asynchronous counter. Design a 3 bit up synchronous counter using T flip flop.

## Short answer

Synchronous counters update all flip-flops simultaneously from a common clock; asynchronous counters ripple. For a 3-bit synchronous up counter with T flip-flops: connect all clocks together; T0 = 1, T1 = Q0, T2 = Q1·Q0. Outputs yield frequencies f/2, f/4, f/8.

## Answer

#### Synchronous vs asynchronous counter
| Point | Synchronous counter | Asynchronous (ripple) counter |
|---|---|---|
| Clock | Common clock to all flip-flops | Only FF0 gets the clock; each next FF is clocked by the previous output |
| Change of state | All flip-flops change together | Flip-flops change one after another (ripple) |
| Delay | One FF delay + gate delay | Adds up: $n \times t_{pd}$ |
| Speed | Fast, high clock frequency | Slow, frequency falls as $n$ grows |
| Circuit | Needs extra gating logic | Simple, few or no extra gates |
| Decoding glitches | None (no false states) | Momentary false states give glitches |
| Example ICs | 74160/74163, 74190 | 7490, 7493 |

#### Design of 3-bit synchronous up counter (T flip-flops)
**Step 1:** Count 000 → 001 → … → 111 → 000. Three T flip-flops ($Q_2Q_1Q_0$) share the clock. A T flip-flop toggles when $T = 1$, so $T = Q \oplus Q^+$.

**Step 2: Excitation table**
| Present Q2Q1Q0 | Next Q2Q1Q0 | T2 | T1 | T0 |
|---|---|---|---|---|
| 000 | 001 | 0 | 0 | 1 |
| 001 | 010 | 0 | 1 | 1 |
| 010 | 011 | 0 | 0 | 1 |
| 011 | 100 | 1 | 1 | 1 |
| 100 | 101 | 0 | 0 | 1 |
| 101 | 110 | 0 | 1 | 1 |
| 110 | 111 | 0 | 0 | 1 |
| 111 | 000 | 1 | 1 | 1 |

**Step 3: K-maps**

| T1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | 0 |

| T2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 |

$T_0 = 1$ in every row.

**Step 4: Equations**
$$
\begin{aligned} &T_2 = Q_1Q_0 \\ &T_1 = Q_0 \\ &T_0 = 1 \end{aligned}
$$

A stage toggles only when all lower bits are 1 (the carry condition).

**Step 5: Circuit diagram**
```text
   +-----+       +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1 T2>|T   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
   |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
T0 = 1    T1 = Q0    T2 = Q1.Q0 (one AND gate)
```

**Step 6: Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   0
```
All outputs change together at the falling clock edge; $Q_0$, $Q_1$, $Q_2$ have frequencies $f/2$, $f/4$, $f/8$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is a synchronous counter faster than an asynchronous (ripple) counter?
   A. It uses fewer gates
   B. All flip-flops share one clock, so the delay is one FF delay plus gate delay instead of n x tpd
   C. It uses JK instead of T flip-flops
   D. It needs no clock
   Answer: B. In a ripple counter the delays of the stages add up (n x tpd), limiting frequency; a common clock avoids this. (Key point: Speed difference)

2. In the 3-bit synchronous up counter with T flip-flops, what are T0 and T1?
   A. T0 = Q0, T1 = Q1
   B. T0 = 1, T1 = Q0
   C. T0 = 1, T1 = Q1Q0
   D. T0 = Q1, T1 = Q2
   Answer: B. The LSB toggles every clock (T0 = 1) and Q1 toggles whenever Q0 = 1. (Key point: T1 and T0 equations)

3. What is T2 for the 3-bit up counter?
   A. T2 = Q1 + Q0
   B. T2 = Q1
   C. T2 = Q1 Q0
   D. T2 = Q2 Q0
   Answer: C. A stage toggles only when all lower bits are 1 (carry condition), so T2 = Q1Q0, one AND gate. (Key point: T2 equation)

4. What are the frequencies of Q0, Q1, Q2 for clock frequency f?
   A. f/2, f/4, f/8
   B. f/8, f/4, f/2
   C. f/2, f/3, f/4
   D. f, f/2, f/4
   Answer: A. Each bit toggles half as often as the one below it, so f/2, f/4 and f/8. (Key point: Frequency division)

## Related in Digital Logic

- [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8
- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
- [Sync vs async; 3-bit Gray code counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Agray-sync-counter-advantages) — Digital Logic, chapter 8
- [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2×
- [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3×
- [3-bit asynchronous up/down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-up-down-counter-3bit) — Digital Logic, chapter 8, asked 2×

## Related in other subjects

- [Structural modelling; 3-bit up counter](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-structural-3bit-counter) — Embedded System, chapter 9
- [Transmission channels; sync vs async](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Atransmission-modes) — Data Communication, chapter 1
- [Multiplexing; synchronous vs asynchronous TDM](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Amux-compare-sync-async-tdm) — Data Communication, chapter 6, asked 6×
- [Synchronous vs asynchronous serial transmission](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-serial) — Microprocessor, chapter 4, asked 3×