---
title: "Synchronous decade counter with timing"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:synchronous-decade-counter"
source: https://www.bctengineer.com/q/semester_3/digital_logic/synchronous-decade-counter
site: BCT Engineering
---

# Synchronous decade counter with timing

Digital Logic · Chapter 8: Counters

- Asked in: 2076 Chaitra, 8 marks; 2069 Chaitra, 8 marks (asked 2 times)
- Video: [Synchronous Decade Counters | decade counter circuit | decade counter timing diagram](https://www.youtube.com/watch?v=Yo2q9qxUac4) — Circus of Physics
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/synchronous-decade-counter
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Design the synchronous decade counter using T flip-flop and also show its timing diagram.

## Short answer

Use four T flip-flops. T0 = 1, T1 = Q3' Q0, T2 = Q1 Q0, T3 = Q3 Q0 + Q2 Q1 Q0. The counter sequences 0000 to 1001 then resets to 0000.

## Answer

A **synchronous decade (BCD / mod-10) counter** counts from 0000 to 1001 (0 to 9) and returns to 0000 on the 10th clock pulse. All flip-flops receive the same clock, so they change state together.

#### Step 1: Number of flip-flops and states
- 10 states are needed, so $2^n \ge 10 \Rightarrow n = 4$ T flip-flops ($Q_3Q_2Q_1Q_0$, $Q_0$ = LSB).
- Used states: 0000 to 1001. Unused states 1010 to 1111 are taken as don't cares (X).
- T flip-flop excitation: $T = Q \oplus Q^+$ (T = 1 whenever the flip-flop must change).

#### Step 2: Excitation table
| Present Q3Q2Q1Q0 | Next Q3Q2Q1Q0 | T3 | T2 | T1 | T0 |
|---|---|---|---|---|---|
| 0000 | 0001 | 0 | 0 | 0 | 1 |
| 0001 | 0010 | 0 | 0 | 1 | 1 |
| 0010 | 0011 | 0 | 0 | 0 | 1 |
| 0011 | 0100 | 0 | 1 | 1 | 1 |
| 0100 | 0101 | 0 | 0 | 0 | 1 |
| 0101 | 0110 | 0 | 0 | 1 | 1 |
| 0110 | 0111 | 0 | 0 | 0 | 1 |
| 0111 | 1000 | 1 | 1 | 1 | 1 |
| 1000 | 1001 | 0 | 0 | 0 | 1 |
| 1001 | 0000 | 1 | 0 | 0 | 1 |

#### Step 3: K-maps (X = don't care)
$T_0 = 1$ for every state. The other inputs:

| T1: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 1 | 1 | 0 |
| 01 | 0 | 1 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | 0 | 0 | X | X |

| T2: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 0 | 1 | 0 |
| 01 | 0 | 0 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | 0 | 0 | X | X |

| T3: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 0 | 0 | 0 |
| 01 | 0 | 0 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | 0 | 1 | X | X |

#### Step 4: Simplified equations
$$
\begin{aligned} &T_3 = Q_3Q_0 + Q_2Q_1Q_0 \\ &T_2 = Q_1Q_0 \\ &T_1 = \overline{Q_3}Q_0 \\ &T_0 = 1 \end{aligned}
$$

So three 2-input AND gates ($\overline{Q_3}Q_0$, $Q_1Q_0$ and $Q_3Q_0$), one 3-input AND gate ($Q_2Q_1Q_0$) and one 2-input OR gate (for $T_3$) are needed.

#### Step 5: Circuit diagram
```text
   +-----+       +-----+       +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1 T2>|T   Q|-Q2 T3>|T   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
   |     |       |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
T0 = 1          T1 = Q3'.Q0
T2 = Q1.Q0      T3 = Q3.Q0 + Q2.Q1.Q0
```

#### Step 6: Timing diagram (negative-edge clock)
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1
```
$Q_0$ toggles on every clock edge, $Q_1$ toggles when $Q_0 = 1$ (except at count 9), $Q_2$ toggles when $Q_1Q_0 = 1$, and $Q_3$ goes high at count 8 and returns low after count 9. The counter therefore divides the clock frequency by 10 ($f_{Q_3} = f_{clk}/10$).

**Self-starting check:** the unused states go back into the count (1010→1011→0110, 1100→1101→0100, 1110→1111→0010), so the counter cannot lock out.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many T flip-flops are used for the decade counter and how are states 1010 to 1111 treated?
   A. 3 flip-flops; as ones
   B. 4 flip-flops; as don't cares
   C. 10 flip-flops; as zeros
   D. 4 flip-flops; as valid states
   Answer: B. 2^n >= 10 gives n = 4, and the six unused states are don't cares in the K-maps. (Key point: Flip-flops and don't cares)

2. Which are the simplified equations for T1 and T2?
   A. T1 = Q3 Q0, T2 = Q2 Q0
   B. T1 = Q3' Q0, T2 = Q1 Q0
   C. T1 = Q0, T2 = Q1
   D. T1 = Q3' Q2, T2 = Q1' Q0
   Answer: B. T1 toggles with Q0 except at count 9 (Q3 = 1), giving Q3'Q0; T2 toggles when Q1Q0 = 1. (Key point: T1 and T2 equations)

3. When does Q3 toggle, and what is T3?
   A. At counts 7 and 9; T3 = Q3 Q0 + Q2 Q1 Q0
   B. At counts 8 and 9; T3 = Q3 + Q0
   C. At count 9 only; T3 = Q3 Q0
   D. At count 7 only; T3 = Q2 Q1 Q0
   Answer: A. Q3 goes 0 to 1 at 0111 (Q2Q1Q0 = 1) and 1 to 0 at 1001 (Q3Q0 = 1), so T3 = Q3Q0 + Q2Q1Q0. (Key point: T3 equation)

4. What are the clocking and output frequency of Q3 in this counter?
   A. Each FF clocked by the previous output; f_clk/8
   B. All FFs share one clock; Q3 has frequency f_clk/10
   C. Only FF0 is clocked; Q3 has frequency f_clk/16
   D. All FFs share one clock; Q3 has frequency f_clk/5
   Answer: B. A synchronous counter uses a common clock, and the 10-state cycle divides the clock by 10. (Key point: Synchronous operation and division)

## Related in Digital Logic

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- [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2×
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## Related in other subjects

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