--- title: "T to JK flip-flop conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:t-to-jk-conversion" source: https://www.bctengineer.com/q/semester_3/digital_logic/t-to-jk-conversion site: BCT Engineering --- # T to JK flip-flop conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2081 Baisakh, 6 marks - Video: [Lec - 40: T flip flop to JK flip flop Conversion | Digital Logic](https://www.youtube.com/watch?v=2M4tZaPiWj4) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/t-to-jk-conversion - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Convert T flip-flop into JK flip-flop. ## Short answer Use the T excitation table and JK characteristic table to build a conversion table. K-map simplification gives T = J·Q' + K·Q. Implement with two AND gates (J with Q', K with Q) feeding an OR gate to the T input; this makes the T flip-flop hold, set, reset, or toggle as required. ## Answer To make a T flip-flop behave as a J-K flip-flop, we add input logic that produces T from J, K and the present state Q. The required J-K behaviour: JK = 00 hold, 01 reset, 10 set, 11 toggle. **Step 1: excitation table of T flip-flop** (T = 1 whenever the state must change) | Q | Q+ | T | |---|---|---| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 | **Step 2: conversion table.** For each J, K and Q, take Q+ from the J-K characteristic table and write the T needed: | J | K | Q | Q+ | T | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | **Step 3: K-map for T** ```text K-map for T Q\JK 00 01 11 10 0 0 0 1 1 1 0 1 1 0 ``` - Group Q = 0, JK = 11 and 10: $J\overline{Q}$. - Group Q = 1, JK = 01 and 11: $KQ$. $$ T = J\,\overline{Q} + K\,Q $$ **Step 4: logic circuit** ```text +-----+ J ------>| | Q' ----->| AND |--+ +-----+ | +----+ +---------+ +->| | | | | OR |---->| T Q |---> Q +->| |CLK->|> T | +-----+ | +----+ | Q' |---> Q' K ------>| | | +---------+ Q ----->| AND |--+ +-----+ (Q and Q' are fed back from the outputs) ``` **Check:** J = K = 1 gives $T = \overline{Q} + Q = 1$ (toggle); J = K = 0 gives T = 0 (hold); J = 1, K = 0 gives $T = \overline{Q}$, so a 0 toggles to 1 and a 1 holds (set); J = 0, K = 1 gives T = Q (reset). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. When must T be 1 in the T flip-flop excitation table? A. Whenever Q+ = 1 B. Whenever Q = 1 C. Whenever the state must change (Q to Q+ differs) D. Whenever the clock is high Answer: C. T = 1 toggles the state, so it is needed exactly when Q+ differs from Q. (Key point: T excitation) 2. What is the input logic for T when converting to J-K? A. T = J Q + K Q' B. T = J Q' + K Q C. T = J + K D. T = J K Answer: B. The K-map groups give T = J Q' + K Q. (Key point: Result) 3. With T = J Q' + K Q, what is T for J = K = 1? A. 0 B. Q C. Q' D. 1, because Q' + Q = 1 Answer: D. T = Q' + Q = 1, so it always toggles. (Key point: J=K=1 check) 4. How is the conversion table built? A. Take Q+ from the J-K characteristic table, then write the T that produces that change B. Take Q+ from the T table, then write J and K C. Copy the S-R table D. Set T equal to J Answer: A. For each J, K, Q find Q+ from the J-K table, then the T needed from the T excitation table. (Key point: Method) ## Close variants set in other exams - [D to JK and JK to D conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ad-to-jk-jk-to-d) — Digital Logic, chapter 6, asked 2× ## Related in Digital Logic - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [JK to SR flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-to-sr-conversion) — Digital Logic, chapter 6 - [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6 - [D and T flip-flops; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ad-t-flipflops-t-to-jk) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× ## Related in other subjects - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9 - [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9