---
title: "3-input XOR using NAND gates only"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:three-input-xor-nand"
source: https://www.bctengineer.com/q/semester_3/digital_logic/three-input-xor-nand
site: BCT Engineering
---

# 3-input XOR using NAND gates only

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2076 Chaitra, 3 marks
- Video: [Implementation of all logic gates with NAND gate | Design with universal gates | digital electronics](https://www.youtube.com/watch?v=4-kCfYGZDtE) — RF Design Basics
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/three-input-xor-nand
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

Realize 3 inputs XOR gates using NAND gates only.

## Short answer

A 3-input XOR is built with eight NAND gates. Two 4-NAND XOR blocks are cascaded: first block computes P = A⊕B using four NANDs (G1= (AB)′, G2= (A G1)′, G3= (B G1)′, G4= (G2 G3)′). Second block similarly computes Y = P⊕C with another four NANDs.

## Answer

A 3-input XOR gives $Y = A \oplus B \oplus C = (A \oplus B) \oplus C$. Each 2-input XOR needs 4 NAND gates, so cascade two 4-NAND XOR blocks: **8 NAND gates**.

**Block 1:** $P = A \oplus B$
$G_1 = \overline{AB}$, $G_2 = \overline{A G_1}$, $G_3 = \overline{B G_1}$, $P = \overline{G_2 G_3}$

**Block 2:** $Y = P \oplus C$
$G_5 = \overline{PC}$, $G_6 = \overline{P G_5}$, $G_7 = \overline{C G_5}$, $Y = \overline{G_6 G_7}$

```text
 A --+-------[G2]--+
     +--[G1]--+    +--[G4]--P--+-------[G6]--+
 B --+-------[G3]--+           +--[G5]--+    +--[G8]-- Y
                           C --+-------[G7]--+
 (all gates are 2-input NAND)
```

| A | B | C | P = A⊕B | Y |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 1 |

Y = 1 when an odd number of inputs are 1.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. 3-input XOR is built from:
   A. Three XNORs
   B. Two cascaded 2-input XOR blocks
   C. One NAND
   D. Two ANDs
   Answer: B. Y = (A xor B) xor C. (Key point: Structure)

2. Total NAND gates:
   A. 6
   B. 5
   C. 8
   D. 4
   Answer: C. 4 per XOR block times two. (Key point: Gate count)

3. Y of 3-input XOR is 1 when:
   A. Even number are 1
   B. All 0
   C. Exactly two 1
   D. An odd number of inputs are 1
   Answer: D. It is an odd-parity function. (Key point: Output meaning)

## Close variants set in other exams

- [2-input XOR using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nor-only) — Digital Logic, chapter 2, asked 2×

## Related in Digital Logic

- [XOR gate using minimum NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nand-only) — Digital Logic, chapter 2, asked 2×
- [De Morgan's laws; XOR using 3-input NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xor-three-input-nand) — Digital Logic, chapter 2
- [De Morgan's laws; XOR from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-xor-nand) — Digital Logic, chapter 2
- [3-input XNOR using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xnor-nor) — Digital Logic, chapter 2
- [Prove De Morgan's theorems; XOR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-prove-xor-nand) — Digital Logic, chapter 2, asked 3×
- [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3

## Related in other subjects

- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6
- [Encoder; NAND and XOR truth tables](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aencoder-truth-tables) — Basic Electronics Engineering, chapter 6
- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6
- [K-map with don't cares, NAND only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-dont-care-nand) — Basic Electronics Engineering, chapter 6