--- title: "Time measurement circuit" subject: "Digital Logic" chapter: 11 key: "semester_3/digital_logic:time-measurement-circuit" source: https://www.bctengineer.com/q/semester_3/digital_logic/time-measurement-circuit site: BCT Engineering --- # Time measurement circuit Digital Logic · Chapter 11: Applications - Asked in: 2081 Bhadra, 5 marks; 2079 Baisakh, 6 marks; 2075 Chaitra, 6 marks; 2075 Asoj, 4 marks (asked 4 times) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/time-measurement-circuit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-11 ## Question With the help of block diagram explain the operation of time measurement circuit. ## Short answer A time measurement circuit counts stable clock pulses during the interval defined by start and stop events. The start sets an S-R flip-flop, opening an AND gate to pass time-base pulses to a decade counter; stop resets the flip-flop. The latched count N gives t = N × Tc, e.g., 1 ms base and 2350 counts yield 2.35 s. ## Answer A **time measurement circuit** (digital timer / period meter) measures the time interval between two events by **counting pulses of a known, accurate clock** during that interval. If a clock of period $T_c$ gives $N$ counts, the measured time is $t = N \times T_c$. #### Block diagram ```text Start ──> ┌──────┐ │ S-R │ Q = gate Stop ──> │ FF │─────────┐ └──────┘ v Crystal ─> Time-base ─> ┌─────┐ oscillator divider │ AND │ └──┬──┘ v Reset ─────────────> ┌──────────────┐ │Decade counter│ └──────┬───────┘ v ┌──────────────┐ │ Latch │ └──────┬───────┘ v ┌──────────────┐ │BCD-to-7-seg │ │dec. + display│ └──────────────┘ ``` #### Blocks 1. **Crystal oscillator** – generates a very stable frequency (e.g. 1 MHz). 2. **Time-base divider** – chain of decade counters (÷10 stages) giving selectable clock periods such as 1 µs, 10 µs, 1 ms. This sets the resolution of the reading. 3. **Start/stop control (S-R flip-flop)** – the start pulse sets the flip-flop ($Q = 1$); the stop pulse resets it ($Q = 0$). So $Q$ is HIGH exactly for the time interval to be measured. 4. **AND gate (main gate)** – passes time-base clock pulses to the counter only while $Q = 1$. 5. **Decade (BCD) counters** – count the pulses passed by the gate. 6. **Latch, decoder and display** – the latch holds the final count; BCD-to-7-segment decoders show it on the display (usually multiplexed). #### Operation 1. Before measurement the counters are reset to zero. 2. The start event sets the flip-flop, opening the AND gate. Clock pulses enter the counter. 3. The stop event resets the flip-flop, closing the gate. Counting stops. 4. The count $N$ is latched and displayed; the time is $t = N \times T_c$, so the display reads directly in µs or ms depending on the selected time base. #### Example With a 1 ms time base, if 2,350 pulses pass the gate, then $$ t = 2350 \times 1\ \text{ms} = 2.35\ \text{s} $$ #### Period measurement For measuring the period of a signal, the input is shaped into pulses and applied to a toggle (divide-by-2) flip-flop; its output stays HIGH for exactly one period and acts as the gate. The accuracy is $\pm 1$ count plus the accuracy of the crystal. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How does a time measurement circuit find a time interval? A. It counts input cycles in a fixed gate B. It counts pulses of a known accurate clock during the interval, t = N x Tc C. It measures the voltage on a capacitor D. It divides the input frequency Answer: B. If N clock pulses of period Tc are counted during the interval, the time is t = N x Tc. (Key point: Principle) 2. What does the S-R flip-flop do in the circuit? A. Start sets it (Q = 1) and stop resets it (Q = 0), so Q is HIGH exactly for the interval B. It counts pulses C. It divides the clock D. It latches the display Answer: A. Q forms the gate signal that is HIGH only between the start and stop events. (Key point: S-R flip-flop role) 3. What sets the resolution of the reading? A. The type of display B. The selected time-base clock period (1 us, 10 us, 1 ms, ...) C. The reset pulse D. The number of latches Answer: B. The divider chain gives selectable clock periods, and a smaller period gives finer resolution. (Key point: Resolution) 4. With a 1 ms time base, 2350 pulses pass the gate. What is the time? A. 2.35 ms B. 23.5 s C. 2.35 s D. 235 ms Answer: C. t = 2350 x 1 ms = 2350 ms = 2.35 s. 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