--- title: "2-input TTL NAND gate" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nand-2input" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nand-2input site: BCT Engineering --- # 2-input TTL NAND gate Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2072 Chaitra, 5 marks - Video: [Transistor Transistor Logic (TTL): TTL NAND Gate Circuit and Working](https://www.youtube.com/watch?v=6Zd582d-PfU) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nand-2input - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw 2-input TTL NAND gate and explain its working principle. ## Short answer When any input is low, Q1's base sits at ~0.9V, Q2 and Q4 are off, Q3 on, output high (~3.4V). When both inputs are high, current through Q1's base-collector turns on Q2 and Q4, Q3 off, output low (~0.2V), giving Y = (AB)'. The totem-pole output ensures fast switching and fan-out of 10. ## Answer A **TTL NAND gate** (7400) is built with bipolar transistors: a multi-emitter input transistor, a phase splitter and a totem-pole output. ```text +5 V +-----------+----------+ | | | R1 4k R2 1.6k R4 130 | | | b +-----+ c A--e Q1 | +--b Q3 B--e c--+ c e +--b Q2 | e D1 | | +-----+ +---- Y | | c R3 1k +--b Q4 | e GND --------+----------+ ``` (b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.) **Circuit parts (standard 7400):** - **Q1 (multi-emitter input transistor):** one emitter per input; works like an AND of diodes. - **Q2 (phase splitter):** gives opposite signals at its collector and emitter to drive the output pair. - **Q3, D1, Q4 (totem-pole output):** Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching. **Operation:** - **Any input LOW (≈ 0.2 V):** that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to forward bias Q1's base–collector junction together with the base–emitter junctions of Q2 and Q4 (that needs about 3 × 0.7 = 2.1 V), so **Q2 and Q4 are OFF**. Q2's collector is pulled up through R2, so **Q3 conducts** as an emitter follower and the output is HIGH (typically about 3.4 V, at least 2.4 V guaranteed). - **All inputs HIGH:** all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2 (Q1's base rises to about 2.1 V), so **Q2 and Q4 saturate**. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so **Q3 is OFF**. | A | B | Q2, Q4 | Q3 | Y | |---|---|---|---|---| | 0 | 0 | OFF | ON | 1 | | 0 | 1 | OFF | ON | 1 | | 1 | 0 | OFF | ON | 1 | | 1 | 1 | ON | OFF | 0 | Hence $Y = \overline{AB}$. Key values: $V_{OH} \approx 3.4$ V (≥ 2.4 V), $V_{OL} \approx 0.2$ V (≤ 0.4 V), propagation delay ≈ 10 ns, power ≈ 10 mW per gate, fan-out 10. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the function of the multi-emitter transistor Q1 in a TTL NAND gate? A. It acts as the phase splitter B. It has one emitter per input and works like an AND of diodes C. It is the active pull-up D. It limits switching current Answer: B. Q1 has one emitter per input and behaves like an AND of diodes; any LOW input conducts through its emitter. (Key point: Multi-emitter input transistor) 2. When any input is LOW, what happens at the output stage? A. Q2 and Q4 saturate and Y is LOW B. Q2 and Q4 are OFF, Q3 conducts and Y is HIGH C. Q3 and Q4 both conduct D. Q3 is OFF and Y is floating Answer: B. Q1's base sits near 0.9 V, so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, turning on Q3 as an emitter follower, so Y is HIGH. (Key point: Any input LOW) 3. When all inputs are HIGH, why is Q3 OFF? A. Q3 is shorted by R4 B. Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base-emitter junction and D1 C. Q1 supplies reverse current to Q3 D. Q4 is OFF Answer: B. With Q2 and Q4 saturated, Q2's collector is about 0.9 V. That cannot forward bias Q3 and D1 together, so Q3 is OFF and Y is LOW. (Key point: All inputs HIGH) 4. What are the roles of D1 and R4 in the totem-pole output? A. D1 keeps Q3 OFF when Q4 is ON; R4 limits the current spike during switching B. D1 sets the input threshold; R4 sets the gate delay C. D1 protects Q1; R4 pulls the input up D. D1 provides the phase split; R4 provides the pull-down Answer: A. D1 adds an extra drop so Q3 stays OFF when Q4 is saturated, and R4 = 130 Ω limits the current when both briefly conduct. (Key point: Role of D1 and R4) ## Related in Digital Logic - [Propagation delay; 2-input TTL NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-ttl-nand) — Digital Logic, chapter 10 - [3-input TTL NAND; totem-pole output](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-3input-totem-pole) — Digital Logic, chapter 10 - [2-input TTL NAND; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NAND gate; transistor switch](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-transistor-switch) — Digital Logic, chapter 10 - [2-input TTL NOR gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-2input) — Digital Logic, chapter 10 - [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10 ## Related in other subjects - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6 - [GPS, components and working principle](https://www.bctengineer.com/question.md?key=semester_4%2Fsurveying_ii%3Agps-components-working-principle) — Surveying II, chapter 8, asked 19× - [Working principle of a digital telephone exchange](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Adigital-telephone-exchange-principle) — Telecommunications, chapter 4, asked 4× - [DC motor working principle and torque equation](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines_i%3Adc-motor-principle-torque-equation) — Electrical Machines I, chapter 4, asked 4×