--- title: "2-input TTL NAND; CMOS characteristics" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nand-cmos-characteristics" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nand-cmos-characteristics site: BCT Engineering --- # 2-input TTL NAND; CMOS characteristics Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2076 Asoj, 4+2 marks - Video: [Transistor Transistor Logic (TTL): TTL NAND Gate Circuit and Working](https://www.youtube.com/watch?v=6Zd582d-PfU) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nand-cmos-characteristics - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw the schematic diagram of 2-input TTL NAND gate and explain about CMOS characteristics. ## Short answer A 2-input TTL NAND gate uses a multi-emitter transistor Q1, phase splitter Q2, and totem-pole output Q3-D1-Q4. Any input low keeps Q2 off and Q3 on, giving Y=1; all inputs high saturate Q2 and Q4, pulling Y=0, so Y = ¬(A·B). CMOS logic has near-zero static power, a wide supply range (3–15 V), noise margins ~30% of VDD, fan-out ~50, but is static-sensitive. ## Answer #### 2-input TTL NAND gate ```text +5 V +-----------+----------+ | | | R1 4k R2 1.6k R4 130 | | | b +-----+ c A--e Q1 | +--b Q3 B--e c--+ c e +--b Q2 | e D1 | | +-----+ +---- Y | | c R3 1k +--b Q4 | e GND --------+----------+ ``` (b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.) **Circuit parts (standard 7400):** - **Q1 (multi-emitter input transistor):** one emitter per input; works like an AND of diodes. - **Q2 (phase splitter):** gives opposite signals at its collector and emitter to drive the output pair. - **Q3, D1, Q4 (totem-pole output):** Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching. **Operation:** - **Any input LOW (≈ 0.2 V):** that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to forward bias Q1's base–collector junction together with the base–emitter junctions of Q2 and Q4 (that needs about 3 × 0.7 = 2.1 V), so **Q2 and Q4 are OFF**. Q2's collector is pulled up through R2, so **Q3 conducts** as an emitter follower and the output is HIGH (typically about 3.4 V, at least 2.4 V guaranteed). - **All inputs HIGH:** all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2 (Q1's base rises to about 2.1 V), so **Q2 and Q4 saturate**. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so **Q3 is OFF**. | A | B | Q2, Q4 | Q3 | Y | |---|---|---|---|---| | 0 | 0 | OFF | ON | 1 | | 0 | 1 | OFF | ON | 1 | | 1 | 0 | OFF | ON | 1 | | 1 | 1 | ON | OFF | 0 | Hence $Y = \overline{AB}$. #### CMOS characteristics - **Very low static power** (nW per gate), since the PMOS and NMOS networks are never ON together; dynamic power $P_D = C_L V_{DD}^2 f$ rises with frequency. - **Wide supply range:** 3–15 V for 4000B, 2–6 V for 74HC. - **High noise margin:** about 30% of $V_{DD}$ (≈ 1.4 V at 5 V); output swings almost rail to rail (≈ 0 V to $V_{DD}$). - **High fan-out** (about 50), as MOS inputs draw almost no current. - **Speed:** 74HC about 8–10 ns delay (similar to LS TTL); 4000B slower (25–100 ns). - **Static sensitive:** inputs must be protected and never left floating. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is Q1 in the 2-input TTL NAND? A. Active pull-up B. Phase splitter C. Clamping diode D. Multi-emitter input transistor acting like an AND of diodes Answer: D. Q2 is the phase splitter; Q3/D1/Q4 form the totem pole. (Key point: Q1 role) 2. What are the output and the state of Q3 when A = B = 1? A. Y = 0 with Q3 OFF and Q2, Q4 saturated B. Y = 1 with Q3 ON C. Y = 0 with Q3 ON D. Y = 1 with Q4 ON Answer: A. Q2's collector near 0.9 V cannot turn on Q3 and D1. (Key point: All inputs HIGH) 3. What is the TTL NAND output HIGH level? A. Exactly 5 V B. About 3.4 V unloaded, at least 2.4 V guaranteed C. About 0.2 V D. About 0.9 V Answer: B. Q3 acts as an emitter follower so the output is below VCC. (Key point: Any input LOW) 4. Which set of CMOS characteristics is correct? A. High static power, narrow supply range, low noise margin B. Low fan-out and high static power C. Very low static power, wide supply range, high noise margin, high fan-out D. Fixed 5 V supply and noise margin of 0.4 V Answer: C. These are the main CMOS strengths. (Key point: CMOS characteristics) 5. Why should CMOS inputs never be left floating? A. They would reduce fan-out to zero B. They cause TTL-style saturation C. They raise the supply voltage D. The gates are static sensitive and floating inputs give unpredictable behaviour Answer: D. Tie unused inputs to VDD or ground. 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