---
title: "TTL NAND gate; transistor switch"
subject: "Digital Logic"
chapter: 10
key: "semester_3/digital_logic:ttl-nand-transistor-switch"
source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nand-transistor-switch
site: BCT Engineering
---

# TTL NAND gate; transistor switch

Digital Logic · Chapter 10: Digital Integrated Circuits

- Asked in: 2075 Asoj, 2+3 marks
- Video: [Transistor Transistor Logic (TTL): TTL NAND Gate Circuit and Working](https://www.youtube.com/watch?v=6Zd582d-PfU) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nand-transistor-switch
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10

## Question

Draw the schematic diagram of TTL NAND gate and explain about the transistor switch.

## Short answer

The TTL NAND gate uses a multi-emitter input transistor; any low input keeps Q2 and Q4 off, Q3 on, giving high output. All inputs high saturate Q2 and Q4, turning Q3 off, output low. A BJT switch is in cut-off (V_BE < 0.7V, open switch, high output) or saturation (I_B ≥ I_C(sat)/β, V_CE ≈ 0.2V, low output).

## Answer

#### TTL NAND gate

```text
              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+
```
(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Any input LOW → Q2, Q4 OFF, Q3 ON → Y = 1; all inputs HIGH → Q2, Q4 saturate, Q3 OFF → Y = 0. So $Y = \overline{AB}$.

#### Transistor as a switch
In digital circuits a BJT is operated only in two regions:

```text
        +VCC
         |
         RC
         |
         +----- Vout
         c
 Vin-RB--b
         e
         |
        GND
```

| Region | Condition | $V_{CE}$ | Acts as |
|---|---|---|---|
| Cut-off | $V_{BE} < 0.7$ V, $I_B = 0$ | ≈ $V_{CC}$ | open switch, Vout HIGH |
| Saturation | $I_B \ge I_{C(sat)}/\beta$ | ≈ 0.2 V | closed switch, Vout LOW |

So the transistor inverts: Vin LOW → OFF → Vout HIGH; Vin HIGH → saturated → Vout LOW.

**Example:** $V_{CC} = 5$ V, $R_C = 1\ \text{k}\Omega$, $\beta = 100$: $I_{C(sat)} = (5 - 0.2)/1\text{k} = 4.8$ mA, so the base current must be at least $4.8\ \text{mA}/100 = 48\ \mu$A for saturation. Switching speed is limited by the time needed to remove stored charge when leaving saturation (storage time).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In cut-off, a BJT switch behaves as:
   A. An open switch with V_CE about VCC, so Vout is HIGH
   B. A closed switch with V_CE about 0.2 V
   C. An open switch with Vout LOW
   D. A closed switch with Vout HIGH
   Answer: A. V_BE < 0.7 V gives I_B = 0, and the transistor is OFF. (Key point: Cut-off)

2. In saturation, V_CE is approximately:
   A. VCC, an open switch
   B. 0.2 V, a closed switch with Vout LOW
   C. 0.7 V, a closed switch with Vout HIGH
   D. 0 V exactly, Vout HIGH
   Answer: B. A saturated transistor pulls Vout near ground. (Key point: Saturation)

3. With VCC = 5 V, RC = 1 k, beta = 100, what minimum base current saturates the transistor?
   A. 4.8 mA
   B. 0.48 mA
   C. 48 microamperes
   D. 480 microamperes
   Answer: C. I_C(sat) = (5-0.2)/1k = 4.8 mA and I_B = 4.8 mA/100 = 48 uA. (Key point: Base current calculation)

4. What limits the BJT switching speed when leaving saturation?
   A. The supply voltage
   B. The number of emitters
   C. The 0.7 V junction drop
   D. Storage time to remove stored charge
   Answer: D. Stored charge must be removed before the transistor turns off. (Key point: Switching speed)

5. What does the TTL NAND do when all inputs are HIGH?
   A. Q2 and Q4 saturate, Q3 is OFF, Y = 0
   B. Q2 and Q4 are OFF, Y = 1
   C. Q3 saturates, Y = 1
   D. Q3 and Q4 are both ON
   Answer: A. Y = (AB)'. (Key point: TTL NAND operation)

## Related in Digital Logic

- [2-input TTL NAND gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-2input) — Digital Logic, chapter 10
- [Propagation delay; 2-input TTL NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-ttl-nand) — Digital Logic, chapter 10
- [2-input TTL NAND; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-cmos-characteristics) — Digital Logic, chapter 10
- [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10
- [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10
- [TTL NOR gate; totem pole](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-totem-pole) — Digital Logic, chapter 10

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- [Power transistor switch and opto-coupler isolation](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_electronics%3Apower-transistor-switch-opto) — Power Electronics, chapter 1
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- [Transistor as a switch](https://www.bctengineer.com/question.md?key=semester_3%2Felectronics_devices_and_circuit%3Abjt-switch-cutoff-saturation) — Electronics Devices and Circuit, chapter 2