--- title: "2-input TTL NOR gate" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nor-2input" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-2input site: BCT Engineering --- # 2-input TTL NOR gate Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2070 Chaitra, 6 marks - Video: [TTL NOR Gate with Totem Pole Output: Circuit and Working](https://www.youtube.com/watch?v=a3xtXuFm1Uk) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-2input - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw the schematic diagram of TTL two input NOR Gate. ## Short answer In the 2-input TTL NOR gate, each input has its own transistor and phase splitter; the splitters are in parallel. If either input is high, that splitter saturates, pulling the common collector low, turning Q3 off and Q4 on, Y=0. Only when both inputs are low, both splitters off, Q3 on, Q4 off, Y=1, so Y = (A+B)'. ## Answer A **TTL NOR gate** (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output. ```text +5 V +-------+--------+----------+ R1A 4k R1B 4k R2 1.6k R4 130 | | | | b b +-----+ c A--e Q1A B-e Q1B | +--b Q3 c c | e | | +--+--+ | | | c c D1 +-------)---b Q2A | | +---------b Q2B | e e +--- Y +--+--+ c | +--b Q4 +-----+ e | | R3 1k | GND -------------+----------+ ``` (")" marks a crossing without connection.) **Circuit (standard 7402):** - Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B). - Q2A and Q2B are connected **in parallel**: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base). - The output stage is the usual **totem pole** Q3, D1, Q4. **Operation:** - **A = 0, B = 0:** both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → **Y = 1** (HIGH). - **A = 1 (B any):** Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which **saturates**. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → **Y = 0**. - **B = 1 (A any):** the same happens through Q1B and Q2B → **Y = 0**. | A | B | Q2A | Q2B | Q3 | Q4 | Y | |---|---|---|---|---|---|---| | 0 | 0 | OFF | OFF | ON | OFF | 1 | | 0 | 1 | OFF | ON | OFF | ON | 0 | | 1 | 0 | ON | OFF | OFF | ON | 0 | | 1 | 1 | ON | ON | OFF | ON | 0 | Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the TTL NOR gate different from the TTL NAND gate in its internal structure? A. It uses a separate input transistor and phase splitter per input, with the phase splitters in parallel B. It uses a multi-emitter transistor with series output transistors C. It has no totem-pole output D. It uses phase splitters in series Answer: A. Each input has its own Q1 and Q2; Q2A and Q2B have collectors joined and emitters joined (parallel), then drive the usual totem pole. (Key point: NOR structure) 2. For A = 0, B = 0, what are the states of Q2A, Q2B, Q3 and Q4? A. Q2A, Q2B ON; Q3 OFF; Q4 ON B. Q2A, Q2B OFF; Q3 ON; Q4 OFF C. Q2A ON, Q2B OFF; Q3 ON; Q4 OFF D. All transistors OFF Answer: B. Both input transistors conduct through their emitters, so neither phase splitter gets base current. Q4 is OFF, Q3 is ON and Y = 1. (Key point: Both inputs LOW) 3. Why is one HIGH input enough to make the output LOW? A. Its phase splitter saturates and alone pulls the common collector line low (Q3 OFF) and drives Q4 ON B. Its input transistor turns Q3 on C. Both phase splitters must saturate D. The HIGH input directly grounds the output Answer: A. Because the phase splitters are in parallel, one saturated Q2 turns Q4 ON and Q3 OFF, so Y = 0. (Key point: One input HIGH) 4. What logic function does the circuit realise and why? A. Y = AB complemented, because splitters are in series B. Y = (A + B) complemented, because the parallel splitters make either HIGH input pull Y LOW C. Y = A + B, because it is non-inverting D. Y = A XOR B Answer: B. Either input HIGH gives Y = 0 and only both LOW gives Y = 1, which is NOR. (Key point: Logic function) ## Related in Digital Logic - [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NOR gate; totem pole](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-totem-pole) — Digital Logic, chapter 10 - [TTL NOR gate; 74XX characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-74xx-characteristics) — Digital Logic, chapter 10 - [TTL NOR gate; propagation delay](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-propagation-delay) — Digital Logic, chapter 10 - [2-input TTL NAND gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-2input) — Digital Logic, chapter 10 - [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10 ## Related in other subjects - [Short note: Ex-OR and Ex-NOR gate](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-xor-xnor) — Basic Electrical and Electronics Engineering, chapter 3 - [Schematic diagram of rural gravity scheme](https://www.bctengineer.com/question.md?key=semester_5%2Fwater_supply_engineering%3Arural-gravity-scheme-diagram) — Water Supply Engineering, chapter 1, asked 5× - [Two-wire 40 Ω line, input and output voltage](https://www.bctengineer.com/question.md?key=semester_3%2Felectromagnetism%3Atwo-wire-40-ohm-line-voltages) — Electromagnetism, chapter 5