--- title: "TTL NOR gate; 74XX characteristics" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nor-74xx-characteristics" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-74xx-characteristics site: BCT Engineering --- # TTL NOR gate; 74XX characteristics Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2068 Baisakh, 6 marks - Video: [TTL Logic: TTL NAND and NOR gates Explained](https://www.youtube.com/watch?v=sDn2hi5ndCA) — ALL ABOUT ELECTRONICS - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-74xx-characteristics - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw the schematic diagram of TTL NOR gate. Discuss the characteristics of TTL 74XX series gates. ## Short answer A TTL NOR gate uses multiple emitter inputs with phase splitters; any input HIGH saturates a phase splitter, turning on Q4 and off Q3, giving Y=0. Standard 74XX characteristics: VCC=5V±5%, VIH=2V, VIL=0.8V, VOH=2.4V, VOL=0.4V, noise margin 0.4V, fan-out 10, propagation delay ~10ns, power ~10mW. ## Answer #### TTL NOR gate ```text +5 V +-------+--------+----------+ R1A 4k R1B 4k R2 1.6k R4 130 | | | | b b +-----+ c A--e Q1A B-e Q1B | +--b Q3 c c | e | | +--+--+ | | | c c D1 +-------)---b Q2A | | +---------b Q2B | e e +--- Y +--+--+ c | +--b Q4 +-----+ e | | R3 1k | GND -------------+----------+ ``` (")" marks a crossing without connection.) Either input HIGH saturates its phase splitter (Q2A or Q2B) → Q4 ON, Q3 OFF → Y = 0. Both inputs LOW → Q2A, Q2B OFF → Q3 ON → Y = 1. So $Y = \overline{A + B}$. #### Characteristics of standard TTL 74XX series | Parameter | Value | |---|---| | Supply voltage | 5 V ± 5% (4.75–5.25 V) | | $V_{IH(min)}$ / $V_{IL(max)}$ | 2.0 V / 0.8 V | | $V_{OH(min)}$ / $V_{OL(max)}$ | 2.4 V / 0.4 V | | Noise margin | 0.4 V | | Input currents | $I_{IH} = 40\ \mu$A, $I_{IL} = -1.6$ mA | | Output currents | $I_{OH} = -400\ \mu$A, $I_{OL} = 16$ mA | | Fan-out | $I_{OL}/I_{IL} = 16/1.6 = 10$ | | Propagation delay | ≈ 9–10 ns | | Power per gate | ≈ 10 mW | | Speed–power product | ≈ 100 pJ | | Temperature range | 0 to 70 °C (54XX: −55 to 125 °C) | Other points: totem-pole output (fast, but outputs cannot be wired together), unconnected inputs act as HIGH (but should be tied to $V_{CC}$ through a resistor), and current spikes during switching need decoupling capacitors. Improved families (74LS, 74S, 74ALS, 74F) trade speed against power. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In the TTL NOR gate, what causes the output to go LOW? A. Both inputs HIGH only B. Either input HIGH, which saturates its phase splitter, turning Q4 ON and Q3 OFF C. Both inputs LOW D. Q3 saturating Answer: B. Any HIGH input saturates its Q2, giving Y = 0. Only both LOW gives Y = 1, which is NOR. (Key point: NOR operation) 2. How is the fan-out of standard TTL calculated and what is it? A. IOL/IIL = 16 mA / 1.6 mA = 10 B. IOH/IIH = 0.4 mA / 40 uA = 10 from the LOW state C. IIL/IOL = 1.6/16 = 0.1 D. VCC/VOL = 12.5 Answer: A. Fan-out is the output sink current divided by the input current in the worse state: 16 mA / 1.6 mA = 10. (Key point: Fan-out) 3. Which set matches standard 74XX values? A. Delay about 100 ns, power about 1 mW B. Delay about 10 ns, power about 10 mW per gate, speed-power product about 100 pJ C. Delay about 1 ns, power about 100 mW D. Delay about 10 us, power about 10 uW Answer: B. Standard TTL has a delay of about 10 ns and about 10 mW per gate, so the speed-power product is about 100 pJ. (Key point: Standard TTL parameters) 4. What is true about unused or unconnected TTL inputs? A. They act as LOW B. They act as HIGH, but should still be tied to VCC through a resistor C. They damage the gate instantly D. They act as the output Answer: B. A floating TTL input acts as HIGH, but it is good practice to tie it to VCC through a resistor to avoid noise pickup. (Key point: Practical points) ## Related in Digital Logic - [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NOR gate; totem pole](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-totem-pole) — Digital Logic, chapter 10 - [2-input TTL NOR gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-2input) — Digital Logic, chapter 10 - [TTL NOR gate; propagation delay](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-propagation-delay) — Digital Logic, chapter 10 - [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2 - [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10 ## Related in other subjects - [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6 - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6 - [Spillway gates and radial gate](https://www.bctengineer.com/question.md?key=semester_6%2Fhydro_power%3Aspillway-gates-radial-gate) — Hydro Power, chapter 6 - [Short note: Ex-OR and Ex-NOR gate](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-xor-xnor) — Basic Electrical and Electronics Engineering, chapter 3