--- title: "TTL NOR gate; CMOS characteristics" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nor-cmos-characteristics" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-cmos-characteristics site: BCT Engineering --- # TTL NOR gate; CMOS characteristics Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2080 Baisakh, 4+3 marks - Video: [TTL Logic: TTL NAND and NOR gates Explained](https://www.youtube.com/watch?v=sDn2hi5ndCA) — ALL ABOUT ELECTRONICS - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-cmos-characteristics - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw and explain the schematic diagram of TTL NOR gate and explain about CMOS characteristics. ## Short answer A TTL NOR gate uses separate input transistors and phase splitters in parallel; output is low if any input is high. CMOS characteristics: near-zero static power, wide supply voltage (3-15V), high noise margin (~1.4V at 5V), rail-to-rail output, high fan-out, and static sensitivity. ## Answer #### TTL NOR gate A **TTL NOR gate** (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output. ```text +5 V +-------+--------+----------+ R1A 4k R1B 4k R2 1.6k R4 130 | | | | b b +-----+ c A--e Q1A B-e Q1B | +--b Q3 c c | e | | +--+--+ | | | c c D1 +-------)---b Q2A | | +---------b Q2B | e e +--- Y +--+--+ c | +--b Q4 +-----+ e | | R3 1k | GND -------------+----------+ ``` (")" marks a crossing without connection.) **Circuit (standard 7402):** - Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B). - Q2A and Q2B are connected **in parallel**: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base). - The output stage is the usual **totem pole** Q3, D1, Q4. **Operation:** - **A = 0, B = 0:** both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → **Y = 1** (HIGH). - **A = 1 (B any):** Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which **saturates**. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → **Y = 0**. - **B = 1 (A any):** the same happens through Q1B and Q2B → **Y = 0**. | A | B | Q2A | Q2B | Q3 | Q4 | Y | |---|---|---|---|---|---|---| | 0 | 0 | OFF | OFF | ON | OFF | 1 | | 0 | 1 | OFF | ON | OFF | ON | 0 | | 1 | 0 | ON | OFF | OFF | ON | 0 | | 1 | 1 | ON | ON | OFF | ON | 0 | Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW. #### CMOS characteristics - **Very low static power** (nW per gate), since the PMOS and NMOS networks are never ON together; dynamic power $P_D = C_L V_{DD}^2 f$ rises with frequency. - **Wide supply range:** 3–15 V for 4000B, 2–6 V for 74HC. - **High noise margin:** about 30% of $V_{DD}$ (≈ 1.4 V at 5 V); output swings almost rail to rail (≈ 0 V to $V_{DD}$). - **High fan-out** (about 50), as MOS inputs draw almost no current. - **Speed:** 74HC about 8–10 ns delay (similar to LS TTL); 4000B slower (25–100 ns). - **Static sensitive:** inputs must be protected and never left floating. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the TTL NOR gate (7402) built? A. A single multi-emitter input with one phase splitter B. Separate input transistor and phase splitter per input, with the phase splitters in parallel, then a totem pole C. Phase splitters in series followed by an open-collector output D. One input transistor feeding two totem poles Answer: B. Q2A and Q2B are in parallel (collectors and emitters joined). (Key point: TTL NOR structure) 2. In the TTL NOR gate, what happens when A = 1 and B = 0? A. Q2A saturates, pulling Q3 off and Q4 on, so Y = 0 B. Both Q2A and Q2B are OFF so Y = 1 C. Q2B saturates but Q4 stays OFF D. Q3 stays ON so Y = 1 Answer: A. Any one saturated phase splitter is enough to turn Q4 ON and Q3 OFF. (Key point: NOR operation) 3. Why does the parallel arrangement give a NOR function? A. Both inputs must be HIGH to pull the output LOW B. The output is HIGH whenever any input is HIGH C. Either input HIGH is enough to pull the output LOW D. Q3 is turned on by any HIGH input Answer: C. Output is HIGH only when A = B = 0, i.e. Y = (A+B)'. (Key point: Why NOR) 4. What is the CMOS noise margin at 5 V? A. About 0.4 V B. About 30% of VDD (about 1.4 V) C. About 10% of VDD D. About 0.8 V Answer: B. CMOS noise margin is much larger than TTL's 0.4 V. (Key point: CMOS noise margin) 5. Which statement about CMOS is correct? A. 4000B works only at 5 V and is faster than 74HC B. 74HC works from 3-15 V C. Both have delays of about 1 ns D. 4000B works from 3-15 V and is slower (25-100 ns) than 74HC (8-10 ns) Answer: D. 4000B has a wide supply and is slow; 74HC is about as fast as LS TTL. (Key point: CMOS speed and supply) ## Related in Digital Logic - [TTL NOR gate; 74XX characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-74xx-characteristics) — Digital Logic, chapter 10 - [CMOS characteristics; TTL 2-input AND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-ttl-and) — Digital Logic, chapter 10 - [2-input TTL NAND; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NOR gate; totem pole](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-totem-pole) — Digital Logic, chapter 10 - [2-input TTL NOR gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-2input) — Digital Logic, chapter 10 - [TTL NOR gate; propagation delay](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-propagation-delay) — Digital Logic, chapter 10 ## Related in other subjects - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [CMOS NAND, NOR (and NOT) circuits](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acmos-nand-nor-circuits) — Embedded System, chapter 8, asked 2× - [Short note: Ex-OR and Ex-NOR gate](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-xor-xnor) — Basic Electrical and Electronics Engineering, chapter 3 - [Schematic diagram of rural gravity scheme](https://www.bctengineer.com/question.md?key=semester_5%2Fwater_supply_engineering%3Arural-gravity-scheme-diagram) — Water Supply Engineering, chapter 1, asked 5×