--- title: "TTL NOR gate; propagation delay" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nor-propagation-delay" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-propagation-delay site: BCT Engineering --- # TTL NOR gate; propagation delay Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2078 Kartik, 4+2 marks - Video: [Propagation Delay in logic gates](https://www.youtube.com/watch?v=m_U0RjcU4jU) — EE Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-propagation-delay - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Explain TTL NOR gate with circuit diagram and truth table. What is a propagation delay? ## Short answer A TTL NOR gate uses separate input transistors with parallel phase splitters and a totem-pole output. Any input high turns on its phase splitter, pulling the output low, so Y = ¬(A+B). Propagation delay is the time from an input change to the corresponding output change measured at the 50% points, averaging tPHL and tPLH (about 9–10 ns for standard TTL). ## Answer #### TTL NOR gate A **TTL NOR gate** (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output. ```text +5 V +-------+--------+----------+ R1A 4k R1B 4k R2 1.6k R4 130 | | | | b b +-----+ c A--e Q1A B-e Q1B | +--b Q3 c c | e | | +--+--+ | | | c c D1 +-------)---b Q2A | | +---------b Q2B | e e +--- Y +--+--+ c | +--b Q4 +-----+ e | | R3 1k | GND -------------+----------+ ``` (")" marks a crossing without connection.) **Circuit (standard 7402):** - Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B). - Q2A and Q2B are connected **in parallel**: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base). - The output stage is the usual **totem pole** Q3, D1, Q4. **Operation:** - **A = 0, B = 0:** both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → **Y = 1** (HIGH). - **A = 1 (B any):** Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which **saturates**. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → **Y = 0**. - **B = 1 (A any):** the same happens through Q1B and Q2B → **Y = 0**. | A | B | Q2A | Q2B | Q3 | Q4 | Y | |---|---|---|---|---|---|---| | 0 | 0 | OFF | OFF | ON | OFF | 1 | | 0 | 1 | OFF | ON | OFF | ON | 0 | | 1 | 0 | ON | OFF | OFF | ON | 0 | | 1 | 1 | ON | ON | OFF | ON | 0 | Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW. #### Propagation delay **Propagation delay** is the time between a change at a gate's input and the resulting change at its output, measured between the 50% points of the two edges. It has two values: $t_{PHL}$ (output falls) and $t_{PLH}$ (output rises); the average is $t_{pd} = (t_{PHL} + t_{PLH})/2$. For standard TTL (7400) $t_{pd} \approx 9$–10 ns. It sets the maximum speed of the gate. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In the 7402 NOR gate, how are the phase splitters Q2A and Q2B connected? A. In parallel, with collectors joined and emitters joined B. In series C. Only Q2A is connected to the output D. Each drives its own separate totem pole Answer: A. Parallel splitters make either HIGH input pull the output LOW. (Key point: TTL NOR structure) 2. With A = B = 0, what is the output and why? A. Y = 0 because both Q2 saturate B. Y = 1 because Q2A and Q2B are OFF, Q4 is OFF and Q3 is ON C. Y = 0 because Q3 is OFF D. Y floats because all transistors are OFF Answer: B. Both Q1 emitters conduct, so no base current reaches Q2A or Q2B. (Key point: A = B = 0) 3. What happens when only B = 1? A. Nothing, because A is LOW B. Q2A saturates C. Q1B's base current enters Q2B, which saturates, turning Q4 ON and Q3 OFF, so Y = 0 D. Q3 turns ON and Y = 1 Answer: C. A single saturated phase splitter is enough. (Key point: One input HIGH) 4. What is propagation delay and how is the average found? A. Time for the supply to settle; average = tPHL x tPLH B. Output rise time only; average = tPLH C. Time between the 10% and 90% points of the output D. Time from input change to output change at 50% points; average = (tPHL + tPLH)/2 Answer: D. It sets the maximum speed of the gate; standard TTL is about 9-10 ns. (Key point: Propagation delay) ## Related in Digital Logic - [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10 - [Propagation delay; 3-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-cmos-nor-3input) — Digital Logic, chapter 10 - [Propagation delay; 2-input TTL NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-ttl-nand) — Digital Logic, chapter 10 - [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NOR gate; totem pole](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-totem-pole) — Digital Logic, chapter 10 - [2-input TTL NOR gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-2input) — Digital Logic, chapter 10 ## Related in other subjects - [Short note: Ex-OR and Ex-NOR gate](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-xor-xnor) — Basic Electrical and Electronics Engineering, chapter 3 - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [TTL to RS-232 interfacing circuit](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Attl-rs232-interface) — Instrumentation II, chapter 3