--- title: "TTL NOR gate; totem pole" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-nor-totem-pole" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-totem-pole site: BCT Engineering --- # TTL NOR gate; totem pole Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2074 Chaitra, 6 marks - Video: [TTL NOR Gate with Totem Pole Output: Circuit and Working](https://www.youtube.com/watch?v=a3xtXuFm1Uk) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-nor-totem-pole - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw the schematic diagram of TTL NOR gate and explain about totem pole. ## Short answer The TTL NOR gate uses separate input transistors and phase splitters connected in parallel. If any input is high, the corresponding phase splitter saturates, turning Q3 off and Q4 on, output low. Only both inputs low yield output high. The totem-pole output (Q3, D1, Q4 stacked) provides low output resistance in both states, fast switching, and low static power since only one conducts. ## Answer #### TTL NOR gate A **TTL NOR gate** (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output. ```text +5 V +-------+--------+----------+ R1A 4k R1B 4k R2 1.6k R4 130 | | | | b b +-----+ c A--e Q1A B-e Q1B | +--b Q3 c c | e | | +--+--+ | | | c c D1 +-------)---b Q2A | | +---------b Q2B | e e +--- Y +--+--+ c | +--b Q4 +-----+ e | | R3 1k | GND -------------+----------+ ``` (")" marks a crossing without connection.) **Circuit (standard 7402):** - Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B). - Q2A and Q2B are connected **in parallel**: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base). - The output stage is the usual **totem pole** Q3, D1, Q4. **Operation:** - **A = 0, B = 0:** both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → **Y = 1** (HIGH). - **A = 1 (B any):** Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which **saturates**. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → **Y = 0**. - **B = 1 (A any):** the same happens through Q1B and Q2B → **Y = 0**. | A | B | Q2A | Q2B | Q3 | Q4 | Y | |---|---|---|---|---|---|---| | 0 | 0 | OFF | OFF | ON | OFF | 1 | | 0 | 1 | OFF | ON | OFF | ON | 0 | | 1 | 0 | ON | OFF | OFF | ON | 0 | | 1 | 1 | ON | ON | OFF | ON | 0 | Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW. #### Totem pole **Totem-pole output** is the TTL output stage in which two transistors are stacked one above the other between $V_{CC}$ and ground, like a totem pole: **Q3 (active pull-up)** on top with R4 = 130 Ω and diode D1, and **Q4 (pull-down)** below. The output Y is taken from their junction. The phase splitter Q2 drives them in opposite phase, so only one is ON at a time. ```text +5 V | R4 130 | c Q2c-b Q3 (ON for HIGH output) e | D1 +------- Y c Q2e-b Q4 (ON for LOW output) e | GND ``` | Output | Q3 | Q4 | Path | |---|---|---|---| | HIGH | ON | OFF | load connected to $V_{CC}$ via R4, Q3, D1 | | LOW | OFF | ON | load connected to ground via Q4 | **Significance:** - **Low output resistance in both states:** Q3 sources current and Q4 sinks current, so load capacitance is charged and discharged quickly → short rise and fall times, higher speed than a resistor pull-up. - **Low power:** in the LOW state Q3 is OFF, so no current flows from $V_{CC}$ through a pull-up into the ON transistor, unlike a passive (resistor) pull-up. - **D1** adds an extra 0.7 V drop so that Q3 stays OFF when Q4 is saturated. - **R4** limits the current spike that flows for a few ns when both transistors are briefly ON during switching. - **Limitation:** totem-pole outputs must not be wired together (wired-AND); if one output is HIGH and another LOW, a large current flows and may damage the gates. Open-collector or tristate outputs are used for bus connections. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In the TTL NOR (7402), what happens when A = 1, B = 0? A. Both Q2A and Q2B stay OFF B. Q2A saturates, Q3 is OFF and Q4 is ON, so Y = 0 C. Q3 is ON and Y = 1 D. Q2B saturates and Q2A is OFF Answer: B. One saturated parallel phase splitter is enough. (Key point: NOR operation) 2. What is a totem-pole output? A. Two transistors in parallel driving separate loads B. A single transistor with a pull-up resistor C. Two transistors stacked between VCC and ground, Q3 pull-up on top and Q4 pull-down below, output at their junction D. A transistor pair that sets Hi-Z Answer: C. The phase splitter drives them in opposite phase so only one is ON. (Key point: Totem-pole definition) 3. Why is a totem pole faster than a resistor pull-up? A. It has lower supply voltage B. It has fewer transistors C. It has no capacitance D. Low output resistance in both states charges and discharges load capacitance quickly Answer: D. Q3 sources and Q4 sinks current actively. (Key point: Totem-pole advantage) 4. What does D1 do in the totem pole? A. Adds a 0.7 V drop so Q3 is surely OFF when Q4 is saturated B. Limits the current spike C. Provides the pull-up path D. Sets the input threshold Answer: A. R4 handles the spike; D1 ensures Q3 stays OFF. (Key point: D1) 5. Why must totem-pole outputs not be wired together? A. They would produce an indeterminate level only B. If one is HIGH and another LOW, a large current flows and may damage the gates C. They would reduce noise margin to zero harmlessly D. They would double fan-out Answer: B. Open-collector or tristate outputs are used for buses. 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