--- title: "TTL OR gate; propagation delay and power" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:ttl-or-propagation-power" source: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-or-propagation-power site: BCT Engineering --- # TTL OR gate; propagation delay and power Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2076 Chaitra, 4+2 marks - Video: [Digital IC Parameters: Propagation Delay, Threshold Voltage, Power Dissipation & Figure of Merits](https://www.youtube.com/watch?v=j0f8rIrRdRI) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ttl-or-propagation-power - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Explain the operation of TTL two input OR gate with schematic diagram and also define the propagation delay time and power dissipation. ## Short answer A TTL OR gate (7432) uses a NOR input stage with parallel phase splitters, then an inverter and totem-pole output, yielding Y = A+B. Propagation delay tpd is the average of low-to-high and high-to-low transition times measured at 50% points (~9–10 ns). Power dissipation is PD = VCC × ICC(avg), where ICC(avg) = (ICCH+ICCL)/2; typically 10 mW per gate. ## Answer #### TTL two-input OR gate A **TTL OR gate** (7432) is a NOR input section (two input transistors Q1A, Q1B with parallel stages Q2A, Q2B) followed by an extra inverting stage Q3 and a totem-pole output Q4–D1–Q5, so the output is the complement of NOR. ```text Input section (NOR stage): +5 V +-------+--------+ R1A 4k R1B 4k R2 4k | | | b b +------- X A--e Q1A B-e Q1B | c c +--+--+ | | c c +-------)---b Q2A | +---------b Q2B e e +--+--+ | R4 1k | GND ``` ```text Output section (common to AND and OR): +5 V +------+------+ R3 1.6k R5 130 | | +------+ c | +----b Q4 c e X -----b Q3 | e D1 | | +------+ +----- Y | | c R6 1k +----b Q5 | e GND -----+-------------+ ``` The joined collectors of Q2A and Q2B (node X) drive the base of Q3; the output section is the same as in a TTL AND gate. **Operation:** - **A = B = 0:** Q1A and Q1B conduct through their emitters, so Q2A and Q2B are **OFF**. Node X rises through R2 and turns **Q3 ON**; Q3 turns **Q5 ON** and Q4 OFF → **Y = 0**. - **A = 1 or B = 1:** the corresponding Q2 **saturates** and pulls node X LOW → **Q3 OFF** → Q5 OFF, Q4 ON → **Y = 1**. | A | B | Q2A or Q2B ON? | Q3 | Y | |---|---|---|---|---| | 0 | 0 | No | ON | 0 | | 0 | 1 | Yes | OFF | 1 | | 1 | 0 | Yes | OFF | 1 | | 1 | 1 | Yes | OFF | 1 | So $Y = A + B$. #### Propagation delay time The time between an input change and the resulting output change, measured at the 50% points: $t_{PHL}$ for a HIGH→LOW output and $t_{PLH}$ for LOW→HIGH; average $t_{pd} = (t_{PHL} + t_{PLH})/2$ (about 9–10 ns for standard TTL). #### Power dissipation The average power a gate takes from the supply: $$ P_D = V_{CC} \times I_{CC(avg)}, \qquad I_{CC(avg)} = \frac{I_{CCH} + I_{CCL}}{2} $$ For a 7400 package, $I_{CCH} = 4$ mA and $I_{CCL} = 12$ mA, so $I_{CC(avg)} = 8$ mA and $P_D = 5 \times 8 = 40$ mW per package, i.e. **10 mW per gate**. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the TTL OR gate (7432) built? A. NAND input section followed by a diode B. Two AND gates in series C. NOR input section followed by an extra inverting stage Q3 and a totem-pole output D. Open-collector NOR with a pull-up Answer: C. Complement of NOR gives OR. (Key point: OR structure) 2. With A = B = 0, why is Y = 0? A. Q2A and Q2B are OFF, node X rises and turns Q3 ON, which turns Q5 ON and Q4 OFF B. Q2A and Q2B saturate and pull Y low C. Q3 is OFF so Q5 conducts D. Q4 conducts and pulls Y low Answer: A. The extra inverter Q3 flips the NOR result. (Key point: A = B = 0) 3. When A = 1 or B = 1, what happens? A. Q3 turns ON so Y = 0 B. A Q2 saturates, pulls X low, Q3 and Q5 turn OFF and Q4 turns ON, so Y = 1 C. All transistors turn OFF D. Q5 turns ON so Y = 0 Answer: B. Y = A + B. (Key point: Any input HIGH) 4. Propagation delay of a gate is measured as the time between which points? A. The 10% and 90% points of the output edge B. The moment power is applied and the output becomes stable C. The 0 V level of the input and the VCC level of the output D. The 50% point of the input edge and the 50% point of the output edge Answer: D. It is the time from the 50% point of the input change to the 50% point of the resulting output change. (Key point: Propagation delay definition) 5. For a 7400 with ICCH = 4 mA and ICCL = 12 mA at VCC = 5 V, what is power per gate? A. 10 mW B. 40 mW C. 20 mW D. 2.5 mW Answer: A. ICC(avg) = 8 mA, P = 5 x 8 = 40 mW per package of 4 gates, so 10 mW per gate. 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