--- title: "Two-input sequential circuit using T" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:two-input-sequential-circuit-t" source: https://www.bctengineer.com/q/semester_3/digital_logic/two-input-sequential-circuit-t site: BCT Engineering --- # Two-input sequential circuit using T Digital Logic · Chapter 9: Sequential Machines - Asked in: 2078 Bhadra, 12 marks - Video: [FSM Example | Draw the sequential circuit using T flip flop | AKTU | KEC 302 | QUES . 2019-20](https://www.youtube.com/watch?v=kT0bCY_RRX8) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/two-input-sequential-circuit-t - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question Design a sequential circuit with T flip-flop and two inputs X and Y. If X=1 and Y=0 the circuit goes through 00 to 01 to 11 to 10. When X=Y=1, the circuit goes through the transition from 00 to 10 to 01 to 11. When X = 0 and Y=1, the circuit goes through 00 to 11 to 10 to 00. When X = Y = 0, the circuit 00 to 01 to 10 to 11 and repeats. ## Short answer A 2-bit counter with T flip-flops uses XY to select the counting mode. The excitation equations are T1 = Q0 X' Y' + Q0' Y + Q1 Q0' X + Q1' Q0 Y' + XY and T0 = Q1 Q0 + Q1 XY + Q1' Q0' Y' + Q1' X' + X' Y'. ## Answer The circuit has 2 flip-flops ($Q_1 Q_0$, $Q_1$ = MSB), two control inputs X, Y, no separate output (the outputs are the states). It is a counter whose counting sequence is chosen by XY. Flip-flops: **T**. **Assumptions:** each sequence returns to 00 after its last state (XY = 10: 10 → 00; XY = 11: 11 → 00; XY = 00: 11 → 00). For XY = 01 the state 01 is not in the given sequence, so it is taken to go to 00 (keeps the circuit from locking). #### State diagram ```text Arc label = XY 00 -10-> 01 -10-> 11 -10-> 10 -10-> 00 00 -11-> 10 -11-> 01 -11-> 11 -11-> 00 00 -01-> 11 -01-> 10 -01-> 00 01 -01-> 00 (assumed) 00 -00-> 01 -00-> 10 -00-> 11 -00-> 00 ``` #### State table (next state) | Present $Q_1 Q_0$ | XY=00 | XY=01 | XY=10 | XY=11 | |---|---|---|---|---| | 00 | 01 | 11 | 01 | 10 | | 01 | 10 | 00 | 11 | 11 | | 10 | 11 | 00 | 00 | 01 | | 11 | 00 | 10 | 10 | 00 | #### Excitation table of T flip-flop | Q | Q+ | T | |---|---|---| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 | T = 1 whenever the flip-flop must change ($T = Q \oplus Q^+$). #### Transition and excitation table | Q1 Q0 | X Y | Q1+ Q0+ | T1 | T0 | |---|---|---|---|---| | 0 0 | 0 0 | 0 1 | 0 | 1 | | 0 0 | 0 1 | 1 1 | 1 | 1 | | 0 0 | 1 0 | 0 1 | 0 | 1 | | 0 0 | 1 1 | 1 0 | 1 | 0 | | 0 1 | 0 0 | 1 0 | 1 | 1 | | 0 1 | 0 1 | 0 0 | 0 | 1 | | 0 1 | 1 0 | 1 1 | 1 | 0 | | 0 1 | 1 1 | 1 1 | 1 | 0 | | 1 0 | 0 0 | 1 1 | 0 | 1 | | 1 0 | 0 1 | 0 0 | 1 | 0 | | 1 0 | 1 0 | 0 0 | 1 | 0 | | 1 0 | 1 1 | 0 1 | 1 | 1 | | 1 1 | 0 0 | 0 0 | 1 | 1 | | 1 1 | 0 1 | 1 0 | 0 | 1 | | 1 1 | 1 0 | 1 0 | 0 | 1 | | 1 1 | 1 1 | 0 0 | 1 | 1 | #### K-maps and simplified equations ```text T1 XY=00 XY=01 XY=11 XY=10 Q1Q0=00 0 1 1 0 Q1Q0=01 1 0 1 1 Q1Q0=11 1 0 1 0 Q1Q0=10 0 1 1 1 T0 XY=00 XY=01 XY=11 XY=10 Q1Q0=00 1 1 0 1 Q1Q0=01 1 1 0 0 Q1Q0=11 1 1 1 1 Q1Q0=10 1 0 1 0 ``` $$ \begin{aligned} T_1 &= Q_0 X' Y' + Q_0' Y + Q_1 Q_0' X + Q_1' Q_0 Y' + X Y \\ T_0 &= Q_1 Q_0 + Q_1 X Y + Q_1' Q_0' Y' + Q_1' X' + X' Y' \end{aligned} $$ #### Logic diagram ```text +---------------+ T1 +------+ X ------>| T-input |------>| FF1 |--+-- Q1 Y ------>| logic | T0 +------+ | +---->| (equations) |------>| FF0 |--+-- Q0 | +---------------+ +------+ | | CLK to both FFs | +------------ Q1, Q0 fed back ----------+ ``` Gates needed: - $T_1$: a 3-input AND for $Q_0 X' Y'$; a 2-input AND for $Q_0' Y$; a 3-input AND for $Q_1 Q_0' X$; a 3-input AND for $Q_1' Q_0 Y'$; a 2-input AND for $X Y$, combined in a 5-input OR gate. - $T_0$: a 2-input AND for $Q_1 Q_0$; a 3-input AND for $Q_1 X Y$; a 3-input AND for $Q_1' Q_0' Y'$; a 2-input AND for $Q_1' X'$; a 2-input AND for $X' Y'$, combined in a 5-input OR gate. **Check:** with XY = 10 from 00 the equations give 00 → 01 → 11 → 10 → 00; with XY = 11, 00 → 10 → 01 → 11 → 00, as required. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many flip-flops are used and what are the outputs? A. Two T flip-flops; the outputs are the states Q1Q0 B. One T flip-flop; the output is Z C. Two flip-flops and a separate Z D. Four T flip-flops Answer: A. The circuit is a 2-bit counter with a selectable sequence; no separate output is needed. (Key point: Structure) 2. Which sequence does XY = 00 give? A. 00, 01, 11, 10 B. 00, 01, 10, 11, then repeats C. 00, 10, 01, 11 D. 00, 11, 10, 00 Answer: B. XY = 00 gives the normal binary up count. (Key point: XY = 00) 3. For XY = 01 the state 01 is not in the sequence; how is it handled? A. It stays at 01 B. It goes to 11 C. It is assumed to go to 00 D. It is a don't care Answer: C. The answer assumes 01 goes to 00 to avoid locking. (Key point: Assumption) 4. The T input for a flip-flop is: A. T = Q+ B. T = Q' C. T = 1 always D. T = Q xor Q+ Answer: D. T = 1 whenever the flip-flop must change. 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