---
title: "Circuit giving 2's complement of a 4-bit number"
subject: "Digital Logic"
chapter: 5
key: "semester_3/digital_logic:twos-complement-generator"
source: https://www.bctengineer.com/q/semester_3/digital_logic/twos-complement-generator
site: BCT Engineering
---

# Circuit giving 2's complement of a 4-bit number

Digital Logic · Chapter 5: Arithmetic Circuits

- Asked in: 2082 Baisakh, 5 marks
- Video: [4.10: Design a four-bit combinational circuit 2’s complementer. (The output generates the 2’s](https://www.youtube.com/watch?v=WdH1IpN26lg) — Dr. Dhiman (Learn the art of problem solving) 
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/twos-complement-generator
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5

## Question

Design a combinational circuit whose input is 4-bit number and output is 2's complement of input number.

## Short answer

Output Y0 = A0, Y1 = A1⊕A0, Y2 = A2⊕(A1+A0), Y3 = A3⊕(A2+A1+A0). Realized with three XOR and two OR gates. This implements the rule: copy bits from LSB up to and including the first 1, then invert all higher bits.

## Answer

The circuit takes a 4-bit number $A_3A_2A_1A_0$ and gives $Y_3Y_2Y_1Y_0$ = its 2's complement ($\overline{A} + 1$, keeping 4 bits).

#### Truth table

| $A_3A_2A_1A_0$ | $Y_3Y_2Y_1Y_0$ | | $A_3A_2A_1A_0$ | $Y_3Y_2Y_1Y_0$ |
|---|---|---|---|---|
| 0000 | 0000 | | 1000 | 1000 |
| 0001 | 1111 | | 1001 | 0111 |
| 0010 | 1110 | | 1010 | 0110 |
| 0011 | 1101 | | 1011 | 0101 |
| 0100 | 1100 | | 1100 | 0100 |
| 0101 | 1011 | | 1101 | 0011 |
| 0110 | 1010 | | 1110 | 0010 |
| 0111 | 1001 | | 1111 | 0001 |

#### Simplified expressions

From K-maps (or from the rule "copy bits up to and including the first 1 from the right, then invert the rest"):

- $Y_0 = 1$ for odd numbers only: $Y_0 = A_0$
- $Y_1 = 1$ for 01, 10 in $A_1A_0$: $Y_1 = A_1 \oplus A_0$
- $Y_2$ equals $A_2$ when $A_1A_0 = 00$, else $A_2'$: $Y_2 = A_2 \oplus (A_1 + A_0)$
- $Y_3$ equals $A_3$ when $A_2A_1A_0 = 000$, else $A_3'$: $Y_3 = A_3 \oplus (A_2 + A_1 + A_0)$

$$
\begin{aligned} Y_0 &= A_0 \\ Y_1 &= A_1 \oplus A_0 \\ Y_2 &= A_2 \oplus (A_1 + A_0) \\ Y_3 &= A_3 \oplus (A_2 + A_1 + A_0) \end{aligned}
$$

#### Circuit

```text
A0 ------------------------------> Y0
A1, A0 ----------[XOR]-----------> Y1
A1, A0 --[OR]--> X1 = A1+A0
A2, X1 ----------[XOR]-----------> Y2
A2, X1 --[OR]--> X2 = A2+A1+A0
A3, X2 ----------[XOR]-----------> Y3
```

Gates: 3 XOR and 2 OR gates (the second OR adds $A_2$ to the first OR output).

**Check:** $A = 0110$: $Y_0 = 0$, $Y_1 = 1\oplus0 = 1$, $Y_2 = 1\oplus1 = 0$, $Y_3 = 0\oplus1 = 1$, so $Y = 1010$, and $16 - 6 = 10 = 1010$. Correct.

(Alternative: invert each bit with NOT gates and add 1 using a 4-bit parallel adder with $C_0 = 1$.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the circuit output?
   A. The 4-bit 2's complement of the input (invert and add 1)
   B. The 1's complement
   C. The input unchanged
   D. Input plus 2
   Answer: A. Y = A' + 1 keeping 4 bits. (Key point: Definition)

2. What is Y0?
   A. A0'
   B. A0
   C. A1 xor A0
   D. A3
   Answer: B. The LSB of the 2's complement equals the input LSB. (Key point: Y0)

3. What is Y1?
   A. A1
   B. A1 A0
   C. A1 xor A0
   D. A1 + A0
   Answer: C. Bit 1 flips only if A0 = 1. (Key point: Y1)

4. What rule summarises the conversion?
   A. Invert all bits
   B. Copy the MSB, invert others
   C. Invert only the LSB
   D. Copy bits up to and including the first 1 from the right, invert the rest
   Answer: D. This is the shortcut for 2's complement. (Key point: Rule)

## Related in Digital Logic

- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [Define combinational logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acombinational-circuit-define) — Digital Logic, chapter 3
- [TTL input and output signal levels](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-signal-levels) — Digital Logic, chapter 10, asked 2×
- [3-input TTL NAND; totem-pole output](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-3input-totem-pole) — Digital Logic, chapter 10
- [Hazards in asynchronous design; 2-bit comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahazards-2bit-comparator) — Digital Logic, chapter 4
- [Two-input sequential circuit using T](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Atwo-input-sequential-circuit-t) — Digital Logic, chapter 9

## Related in other subjects

- [Input/output interface unit design factors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-interface-unit-importance) — Instrumentation II, chapter 7
- [5-bit R-2R DAC output for 10110](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ar2r-5bit-10110) — Advanced Electronics, chapter 3
- [4-bit R-2R ladder bit voltages and 1011 output](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ar2r-4bit-12v-1011) — Advanced Electronics, chapter 3
- [Bipolar DAC output and 3-bit transfer curve](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Abipolar-dac-transfer-curve) — Advanced Electronics, chapter 3