--- title: "Types of registers" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:types-of-registers" source: https://www.bctengineer.com/q/semester_3/digital_logic/types-of-registers site: BCT Engineering --- # Types of registers Digital Logic ยท Chapter 7: Registers - Asked in: 2070 Chaitra, 8 marks - Video: [Introduction to Registers | What is Shift Register? Types of Shift Registers](https://www.youtube.com/watch?v=bAQfPQqKCHs) โ€” ALL ABOUT ELECTRONICS - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/types-of-registers - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Describe different types of registers with diagram. ## Short answer SISO (serial in/out) passes data through a chain, causing delay. SIPO (serial in, parallel out) converts serial data to a parallel word after n clocks. PISO (parallel in, serial out) loads all bits at once then shifts them out serially. PIPO (parallel in/out) stores data without shifting, acting as a buffer. ## Answer A **register** is a group of flip-flops (usually D type) with a common clock that stores a binary word; an n-bit register has n flip-flops. A **shift register** can also move the stored bits left or right at each clock. Registers are classified by how data is entered and taken out. #### 1. Serial In Serial Out (SISO) Data enters one bit per clock at FF-A and leaves one bit per clock from FF-D. ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-->|D QB|-->|D QC|-->|D QD|--> Dout |> | |> | |> | |> | +-----+ +-----+ +-----+ +-----+ ^ ^ ^ ^ CLK ----+---------+---------+---------+ ``` A 4-bit SISO takes 4 clocks to load and 4 to empty; used as a delay line. #### 2. Serial In Parallel Out (SIPO) Data enters serially; after n clocks all bits are read at once from QA to QD. ```text Din +-----+ +-----+ +-----+ +-----+ ---->|D QA|-+>|D QB|-+>|D QC|-+>|D QD|-+ |> | | |> | | |> | | |> | | +-----+ | +-----+ | +-----+ | +-----+ | ^ | ^ | ^ | ^ | CLK ----+----|----+----|----+----|----+ | v v v v QA QB QC QD (parallel outputs read together) ``` Used for serial-to-parallel conversion (e.g. serial receiver). #### 3. Parallel In Serial Out (PISO) All bits are loaded together when SH/LD' = 0; with SH/LD' = 1 they are shifted out one per clock at QD. ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` Used for parallel-to-serial conversion (e.g. serial transmitter). #### 4. Parallel In Parallel Out (PIPO) Each flip-flop has its own input and output; at one clock edge the whole word is stored and is immediately available. There is no shifting. ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ |D | |D | |D | |D | |> Q| |> Q| |> Q| |> Q| +-----+ +-----+ +-----+ +-----+ ^ | ^ | ^ | ^ | CLK QA QB QC QD (common clock; no connection between stages) ``` Used as a storage (buffer) register, e.g. accumulator or latch for data. #### 5. Bidirectional and universal shift registers - **Bidirectional:** a control line (RIGHT/LEFT') selects shifting right ($D_B = Q_A$) or left ($D_B = Q_C$) through AND-OR gates. - **Universal (e.g. IC 74194):** can hold, shift right, shift left and parallel load, selected by mode inputs S1 S0 (00 hold, 01 shift right, 10 shift left, 11 load). | Type | Data in | Data out | Clocks to load / read (4-bit) | |---|---|---|---| | SISO | Serial | Serial | 4 / 4 | | SIPO | Serial | Parallel | 4 / 0 | | PISO | Parallel | Serial | 1 / 4 | | PIPO | Parallel | Parallel | 1 / 0 | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How are registers classified into SISO, SIPO, PISO and PIPO? A. By the number of flip-flops B. By the clock frequency C. By the type of flip-flop used D. By how data is entered and taken out Answer: D. The names state input mode then output mode. (Key point: Classification) 2. What is special about a PIPO register? A. All bits stored at one clock edge, no shifting B. Bits shift one place per clock C. It has only one flip-flop D. It needs 4 clocks to load Answer: A. Each FF has its own input and output, with no stage connections. (Key point: PIPO) 3. Clocks to load / read a 4-bit PISO register? A. 4 to load and 0 to read B. 1 to load and 4 to read C. 4 to load and 4 to read D. 1 to load and 0 to read Answer: B. PISO loads in parallel (1 clock) and reads serially (4 clocks). (Key point: Clock count) 4. In IC 74194, what does mode S1 S0 = 11 do? A. Hold B. Shift right C. Parallel load D. Shift left Answer: C. 00 hold, 01 shift right, 10 shift left, 11 parallel load. (Key point: Universal register) ## Related in Digital Logic - [Shift register uses; 4-bit ring counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aring-counter-4bit) โ€” Digital Logic, chapter 7 - [Synchronous MOD-5 counter; counter applications](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-applications) โ€” Digital Logic, chapter 8