---
title: "XOR gate using minimum NAND gates"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:xor-using-nand-only"
source: https://www.bctengineer.com/q/semester_3/digital_logic/xor-using-nand-only
site: BCT Engineering
---

# XOR gate using minimum NAND gates

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2073 Shrawan, 5 marks; 2072 Chaitra, 4 marks (asked 2 times)
- Video: [Implementation of all logic gates with NAND gate | Design with universal gates | digital electronics](https://www.youtube.com/watch?v=4-kCfYGZDtE) — RF Design Basics
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/xor-using-nand-only
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

Construct two input XOR gate using minimum number of 2-input NAND gates only.

## Short answer

XOR is built with four 2-input NAND gates: G1 = NAND(A,B), G2 = NAND(A,G1), G3 = NAND(B,G1), and output Y = NAND(G2,G3). This yields A ⊕ B.

## Answer

An XOR gate gives $Y = A \oplus B = A\bar B + \bar A B$. With NAND gates only, the minimum is **four 2-input NAND gates**.

**Derivation**

$$
\begin{aligned} Y &= A\bar B + \bar A B \\ &= A\bar A + A\bar B + B\bar A + B\bar B \quad (\text{adding } A\bar A = B\bar B = 0) \\ &= A(\bar A + \bar B) + B(\bar A + \bar B) \\ &= A\,\overline{AB} + B\,\overline{AB} \\ &= \overline{\overline{A\,\overline{AB}} \cdot \overline{B\,\overline{AB}}} \quad (\text{De Morgan}) \end{aligned}
$$

So the gates are:
- $G_1 = \overline{AB}$
- $G_2 = \overline{A \cdot G_1}$
- $G_3 = \overline{B \cdot G_1}$
- $Y = \overline{G_2 \cdot G_3}$

**Circuit**

```text
 A --+-----------------|‾‾\
     |                 |G2 |o--+
     |  |‾‾\      +----|__/    |   |‾‾\
     +--|G1 |o----+            +---|G4 |o-- Y
     +--|__/      +----|‾‾\    +---|__/
     |                 |G3 |o--+
 B --+-----------------|__/
```

**Verification**

| A | B | $G_1$ | $G_2$ | $G_3$ | Y |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 0 |

Output Y is 1 only when the inputs differ, which is the XOR function. Total: 4 NAND gates.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Minimum number of 2-input NANDs for XOR?
   A. 3
   B. 5
   C. 4
   D. 2
   Answer: C. Four are needed. (Key point: Minimum)

2. What is G1?
   A. A+B
   B. (AB)'
   C. (A+B)'
   D. AB
   Answer: B. G1 feeds both G2 and G3. (Key point: G1)

3. What is G2?
   A. (A G1)'
   B. (A B)'
   C. (G1 B)'
   D. A G1
   Answer: A. A goes to G2, B to G3. (Key point: G2)

4. Final gate G4 computes?
   A. (G2+G3)'
   B. G1 G2
   C. A + B
   D. (G2 G3)' = A xor B
   Answer: D. It gives A B' + A' B. (Key point: Final)

## Related in Digital Logic

- [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2×
- [2-input XOR using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nor-only) — Digital Logic, chapter 2, asked 2×
- [De Morgan's laws; XOR using 3-input NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xor-three-input-nand) — Digital Logic, chapter 2
- [De Morgan's laws; XOR from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-xor-nand) — Digital Logic, chapter 2
- [Prove De Morgan's theorems; XOR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-prove-xor-nand) — Digital Logic, chapter 2, asked 3×
- [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2

## Related in other subjects

- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6
- [Encoder; NAND and XOR truth tables](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aencoder-truth-tables) — Basic Electronics Engineering, chapter 6
- [Perceptron; neural network as XOR gate](https://www.bctengineer.com/question.md?key=semester_6%2Fartificial_intelligence%3Aperceptron-xor-gate) — Artificial Intelligence, chapter 6, asked 2×
- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6