---
title: "2-input XOR using NOR gates only"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:xor-using-nor-only"
source: https://www.bctengineer.com/q/semester_3/digital_logic/xor-using-nor-only
site: BCT Engineering
---

# 2-input XOR using NOR gates only

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2082 Shrawan, 3 marks
- Video: [BEE 313 Implementation of EX OR Gate using NAND and NOR Gates](https://www.youtube.com/watch?v=exmI817CbEg) — Lectures in Electrical Engineering
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/xor-using-nor-only
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

Realize 2 inputs XOR gates using NOR gates only.

## Short answer

An XOR gate can be implemented with five NOR gates. First, four NOR gates produce XNOR: G1 = (A+B)′, G2 = (A+G1)′, G3 = (B+G1)′, G4 = (G2+G3)′ = A⊙B. Then a fifth NOR with both inputs tied to G4 inverts it to yield Y = (G4+G4)′ = A⊕B.

## Answer

$Y = A \oplus B$. Build XNOR with 4 NOR gates and invert it with a fifth NOR (inputs tied). Minimum: **5 NOR gates**.

$$
\begin{aligned} G_1 &= \overline{A + B} \\ G_2 &= \overline{A + G_1} = \bar A B \\ G_3 &= \overline{B + G_1} = A \bar B \\ G_4 &= \overline{G_2 + G_3} = \overline{A \oplus B} \\ Y &= \overline{G_4 + G_4} = A \oplus B \end{aligned}
$$

```text
 A --+-----------[NOR G2]--+
     |              |      |
     +--[NOR G1]----+      +--[NOR G4]--[NOR G5]-- Y
     |              |      |          (inputs tied)
 B --+-----------[NOR G3]--+
```

| A | B | $G_1$ | $G_2$ | $G_3$ | $G_4$ | Y |
|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Minimum number of NOR gates for a 2-input XOR?
   A. 4
   B. 3
   C. 6
   D. 5
   Answer: D. Four NORs form XNOR and a fifth inverts it. (Key point: Gate count)

2. What is G1?
   A. (A+B)'
   B. A'
   C. (AB)'
   D. A xor B
   Answer: A. G1 = NOR(A,B), shared by G2 and G3. (Key point: First gate)

3. Why is the fifth NOR (inputs tied) used?
   A. To make A'
   B. To invert the XNOR output into XOR
   C. To make the OR
   D. To add enable
   Answer: B. G4 = XNOR, so Y = (G4+G4)' = XOR. (Key point: Why final NOR)

## Close variants set in other exams

- [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2×

## Related in Digital Logic

- [3-input XNOR using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xnor-nor) — Digital Logic, chapter 2
- [F = (A+B)(C+D)E using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Anor-only-function-realize) — Digital Logic, chapter 2
- [XOR gate using minimum NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nand-only) — Digital Logic, chapter 2, asked 2×
- [De Morgan's laws; XOR using 3-input NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xor-three-input-nand) — Digital Logic, chapter 2
- [Seven-segment "a" segment using NOR gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aa-segment-nor-gates) — Digital Logic, chapter 4
- [De Morgan's laws; XNOR using NOR gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xnor-nor) — Digital Logic, chapter 2

## Related in other subjects

- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6
- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6