--- title: "555 astable multivibrator and duty cycle" subject: "Electronics Devices and Circuit" chapter: 5 key: "semester_3/electronics_devices_and_circuit:555-astable-duty-cycle" source: https://www.bctengineer.com/q/semester_3/electronics_devices_and_circuit/555-astable-duty-cycle site: BCT Engineering --- # 555 astable multivibrator and duty cycle Electronics Devices and Circuit · Chapter 5: Signal Generator and Waveform-Shaping Circuits - Asked in: 2082 Baisakh, 2+3 marks - Video: [Adjust the Frequency & Duty Cycle of the Astable Multivibrator](https://www.youtube.com/watch?v=xnU2qtv7Rso) — Skinny R&D - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/electronics_devices_and_circuit/555-astable-duty-cycle - Whole chapter: https://www.bctengineer.com/md/semester_3/electronics_devices_and_circuit/chapter-5 ## Question Explain the operation of astable multivibrator using 555 timer IC square wave generator and derive its duty cycle. ## Short answer In 555 astable mode, the capacitor charges through RA+RB (output HIGH) and discharges through RB (output LOW). The duty cycle is D = (RA+RB)/(RA+2RB). Since RA>0, D always exceeds 50%. ## Answer #### Circuit ```text +VCC +-----+-----+ | | | [RA] (4)(8) | | | +--- (7) discharge | [RB] | (6) threshold +------(2) trigger | [C] (3) output | GND (5) via 0.01 µF to GND ``` Pins 2 and 6 are tied together at the capacitor, and the capacitor charges through RA + RB and discharges through RB into pin 7. #### Operation The comparators have thresholds of 2VCC/3 (upper) and VCC/3 (lower). 1. Capacitor charges from VCC/3 to 2VCC/3 through (RA + RB). Output is HIGH, and the discharge transistor is OFF. 2. At 2VCC/3, the upper comparator resets the flip-flop; output goes LOW and the discharge transistor turns ON. 3. The capacitor discharges through RB to VCC/3. At VCC/3, the lower comparator sets the flip-flop and the cycle repeats. #### Duty cycle From the charge and discharge analysis: - HIGH time: tH = 0.693 (RA + RB) C - LOW time: tL = 0.693 RB C - Period: T = tH + tL = 0.693 (RA + 2RB) C **Duty cycle D = tH/T = (RA + RB) / (RA + 2RB)**, usually written as a percentage. Since RA > 0, D is always more than 50 %. When RA << RB, D approaches 50 %; for example, RA = 1 kΩ and RB = 100 kΩ gives D = 50.2 %. When RB << RA, D tends towards 100 %. **Example:** RA = 4.7 kΩ, RB = 10 kΩ, C = 0.1 µF: D = 14.7/24.7 = 59.5 %, f = 1.44/(24.7 kΩ × 0.1 µF) = 583 Hz. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What are the 555 comparator thresholds in the astable circuit? A. VCC/3 (lower) and 2VCC/3 (upper) B. VCC/2 and VCC C. 0 and VCC/3 D. 2VCC/3 and VCC Answer: A. The capacitor swings between VCC/3 and 2VCC/3. (Key point: Thresholds) 2. Through which resistances does the capacitor charge and discharge? A. Charge via RB, discharge via RA + RB B. Charge via RA + RB, discharge via RB C. Both via RA D. Charge via RA, discharge via RA + RB Answer: B. Charging passes through RA + RB while pin 7 discharges through RB only. (Key point: Charge and discharge paths) 3. What is the duty cycle? A. RB/(RA + 2RB) B. (RA + RB)/(RA + 2RB) C. RA/(RA + RB) D. (RA + 2RB)/(RA + RB) Answer: B. D = tH/T = 0.693(RA + RB)C / 0.693(RA + 2RB)C. (Key point: Duty cycle) 4. Why is the duty cycle always more than 50 %? A. Capacitor charges through RA + RB but discharges only through RB B. The upper threshold is above VCC C. Pin 5 adds delay D. The output stage is asymmetrical Answer: A. tH includes RA so tH > tL for any RA > 0. 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