---
title: "JFET DC operating point (IDSS 12 mA, VP -4 V)"
subject: "Electronics Devices and Circuit"
chapter: 3
key: "semester_3/electronics_devices_and_circuit:jfet-dc-operating-point-420k-180k"
source: https://www.bctengineer.com/q/semester_3/electronics_devices_and_circuit/jfet-dc-operating-point-420k-180k
site: BCT Engineering
---

# JFET DC operating point (IDSS 12 mA, VP -4 V)

Electronics Devices and Circuit · Chapter 3: Field-Effect Transistor

- Asked in: 2074 Chaitra, 8 marks
- Video: [Voltage Divider Bias JFET | Calculate Current & Voltage | JFET Biasing Tutorial 15](https://www.youtube.com/watch?v=cGKTGTEwVYo) — Mathematics First
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/electronics_devices_and_circuit/jfet-dc-operating-point-420k-180k
- Whole chapter: https://www.bctengineer.com/md/semester_3/electronics_devices_and_circuit/chapter-3

## Question

Find the DC operating point of JFET circuit given below. Given parameters IDSS = 12 mA and VP = -4V.
[Figure: n-channel JFET amplifier with VDD = 20 V; gate divider R1 = 420 kΩ from VDD to gate and R2 = 180 kΩ from gate to ground; RD = 2.7 kΩ; RS = 2.7 kΩ with bypass capacitor Cs; input coupling capacitor Cc1 and output coupling capacitor Cc2 to RL = 4 kΩ]

## Short answer

VG = 6 V, VGS = 6 – 2.7ID. Using ID = 12(1+VGS/4)², the valid solution is IDQ = 2.97 mA, VGSQ = –2.01 V. VDSQ = 20 – 2.97(2.7+2.7) = 3.98 V. VDS > VGS–VP (1.99 V), so in saturation.

## Answer

**Given:** VDD = 20 V, R1 = 420 kΩ, R2 = 180 kΩ, RD = RS = 2.7 kΩ, IDSS = 12 mA, VP = −4 V. Capacitors are open for dc, so RL and the coupling capacitors do not affect the bias.

#### Step 1: Gate voltage
VG = VDD · R2/(R1 + R2) = 20 × 180/600 = **6 V**

#### Step 2: Bias equations
VGS = VG − ID RS = 6 − 2.7 ID

ID = IDSS (1 − VGS/VP)² = 12 (1 + VGS/4)²

Substituting VGS: 1 + (6 − 2.7 ID)/4 = 2.5 − 0.675 ID

ID = 12 (2.5 − 0.675 ID)²

5.4675 ID² − 41.5 ID + 75 = 0

ID = 4.62 mA or 2.97 mA

For ID = 4.62 mA, VGS = 6 − 12.48 = −6.48 V, which is more negative than VP (the channel would be cut off), so this root is rejected.

#### Step 3: Operating point
- **IDQ = 2.97 mA**
- **VGSQ** = 6 − 2.7 × 2.967 = **−2.01 V**
- **VDSQ** = VDD − ID (RD + RS) = 20 − 2.967 × 5.4 = **3.98 V**

Other voltages: VS = 8.01 V, VD = 11.99 V.

#### Check of region
VDS(sat) = VGS − VP = −2.01 + 4 = 1.99 V. Since VDS = 3.98 V > 1.99 V, the JFET is in the pinch-off (saturation) region and the square-law formula is valid.

**Answer: Q point = (VDS = 3.98 V, ID = 2.97 mA), with VGS = −2.01 V.**

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why do RL and the coupling capacitors not affect the dc bias?
   A. Capacitors are open for dc, isolating RL
   B. RL is zero
   C. They are in series with the source
   D. JFETs ignore loads
   Answer: A. For dc the capacitors are open circuits, so RL is disconnected. (Key point: Effect of RL and capacitors)

2. VG for R1 = 420 kΩ, R2 = 180 kΩ, VDD = 20 V is:
   A. 6 V
   B. 14 V
   C. 9 V
   D. 3 V
   Answer: A. VG = 20*180/600 = 6 V. (Key point: Gate voltage)

3. Why is ID = 4.62 mA rejected?
   A. It gives VGS = -6.48 V, more negative than VP = -4 V
   B. It is below IDSS
   C. It gives VDS = 0
   D. It exceeds 5 mA
   Answer: A. VGS must lie between VP and 0, so the root giving -6.48 V is not physical. (Key point: Valid root)

4. With VGS = -2.01 V and VP = -4 V, VDS(sat) is:
   A. 1.99 V, and VDS = 3.98 V exceeds it, so pinch-off
   B. 6.01 V, so ohmic
   C. 3.98 V
   D. -2.01 V
   Answer: A. VDS(sat) = VGS - VP = 1.99 V < 3.98 V, so the JFET is in saturation. (Key point: Region check)

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