--- title: "Count up/down and tracking type ADC" subject: "Advanced Electronics" chapter: 3 key: "semester_4/advanced_electronics:count-up-down-tracking-adc" source: https://www.bctengineer.com/q/semester_4/advanced_electronics/count-up-down-tracking-adc site: BCT Engineering --- # Count up/down and tracking type ADC Advanced Electronics · Chapter 3: Digital-to-Analog and Analog-to-Digital Conversion - Asked in: 2068 Chaitra, 7 marks - Video: [up/down counter type ADC || tracking type ADC || servo type ADC / analog to digital converter](https://www.youtube.com/watch?v=WVJfYWOjZoI) — POLY KNOWLEDGE - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/count-up-down-tracking-adc - Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-3 ## Question Explain the operation principle of count up/down and tracking type ADC with necessary diagram. ## Short answer Tracking ADC uses up/down counter and comparator: if Vin > V_DAC, counter counts up; if Vin < V_DAC, counts down. After first lock, it tracks the input with ±1 LSB ripple. Fast for slow signals; slew limited to LSB·f₆ₗₖ. ## Answer A tracking (servo or up/down counter) ADC is an improved counter-type ADC. It uses an **up/down counter** in place of the up counter, so the DAC output follows (tracks) the input continuously. It does not restart from zero for each conversion. #### Block diagram ```text Vin -------------------(+)\ >-- comparator --+ +-------------- (-)/ | U/D | v | +------------------------------+ | | n-bit UP/DOWN COUNTER |<-CLOCK | +------------------------------+ | | D(n-1)..D0 | +------------> digital output | v +--------- [ n-bit DAC ] V_DAC ``` #### Working 1. The comparator compares Vin with the DAC output V_DAC. 2. **If Vin > V_DAC:** the comparator output is HIGH, the counter is set to **count up**, and V_DAC rises one step per clock. 3. **If Vin < V_DAC:** the comparator output is LOW, the counter **counts down**, and V_DAC falls one step per clock. 4. At the first conversion the counter climbs from zero like a simple counter ADC. After that, the counter only changes by the amount Vin has changed, so the next conversion takes just a few clock pulses. 5. When V_DAC reaches Vin, the output toggles up and down by ±1 LSB around the correct value. This is the steady-state "bit bobble". The counter contents give the digital value of Vin at any instant. ```text V | Vin | ............................... | _ _ _ _ _ | _| |_| |_| |_| |_| |_ | _| | _| V_DAC toggles ±1 LSB | _| about Vin once locked | _| | _| V_DAC climbs 1 LSB per clock | _| +--------------------------------------- t first lock tracking ``` #### Features - **Fast for slowly varying signals:** the conversion time after locking is a few clocks, not up to 2ⁿ. - Continuous output, with no START pulse needed each time. - **Limitation:** if Vin changes faster than 1 LSB per clock (slew limit = LSB × fclk), the counter cannot follow and the output lags. - The ±1 LSB toggling at steady state needs a latch or display hold. - Uses: tracking slowly changing signals in control systems, servo systems and data loggers. #### Comparison with simple count-up ADC | Count-up ADC | Up/down tracking ADC | |---|---| | Resets to zero every conversion | Never resets, follows Vin | | Conversion time up to 2ⁿ clocks | Few clocks after first lock | | Needs START pulse | Continuous operation | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In a tracking ADC, what does the counter do when Vin > V_DAC? A. Counts down B. Counts up so V_DAC rises one step per clock C. Resets to zero D. Stops Answer: B. A HIGH comparator output sets the counter to count up, raising V_DAC toward Vin. (Key point: Counter direction) 2. What is the main advantage of the tracking ADC over the simple counter ADC? A. It needs no DAC B. It does not restart from zero, so after locking a conversion takes only a few clocks C. It has higher resolution D. It needs a START pulse each time Answer: B. The counter only changes by the amount Vin changed, so conversion after lock is fast. (Key point: Advantage over count-up ADC) 3. What does the digital output do when V_DAC has reached a steady Vin? A. Stays fixed exactly B. Toggles by about +-1 LSB around the correct value C. Drifts to zero D. Overflows Answer: B. The 'bit bobble' of +-1 LSB occurs, so a latch or display hold is needed. (Key point: Steady-state behaviour) 4. When does a tracking ADC fail to follow the input? A. When Vin changes faster than 1 LSB per clock (LSB x fclk) B. When Vin is constant C. When Vin is below Vref D. When the clock is slow only at start Answer: A. The counter can change by only 1 LSB per clock, so faster inputs make the output lag. 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