---
title: "Counter-type ADC numerical (VFS = 12 V)"
subject: "Advanced Electronics"
chapter: 3
key: "semester_4/advanced_electronics:counter-adc-12v-numerical"
source: https://www.bctengineer.com/q/semester_4/advanced_electronics/counter-adc-12v-numerical
site: BCT Engineering
---

# Counter-type ADC numerical (VFS = 12 V)

Advanced Electronics · Chapter 3: Digital-to-Analog and Analog-to-Digital Conversion

- Asked in: 2072 Kartik, 2+2+3 marks
- Video: [Counter Type ADC: Basics, Structure, Working, Conversion Graph, and Conversion Time](https://www.youtube.com/watch?v=O_AWkEGBETc) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/counter-adc-12v-numerical
- Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-3

## Question

For the ADC shown below, the full scale output voltage (VFS) = 12.00V. The clock PRF is 10KHz. Determine: i) Maximum and minimum conversion time ii) Resolution iii) The output count and the conversion time for Vin = 4.25V. [Figure: 4-bit counter (count-up) type ADC: a comparator (+V supply, GND) compares Vin with the DAC output; the comparator output and the CLOCK feed an AND gate that clocks a 4-bit UP COUNTER (outputs D0 (LSB), D1, D2, D3 (MSB), cleared by START); the counter outputs drive a 4-bit DAC whose output returns to the comparator; the comparator output is also the EOC signal.]

## Short answer

Resolution = 12/(2^4−1)=0.8 V. Max time = 15×0.1 ms=1.5 ms, min=0.1 ms. For 4.25 V, floor(4.25/0.8)+1=6 → output 0110, conversion time 0.6 ms.

## Answer

In a counter (count-up) type ADC, the counter starts from zero at START and counts clock pulses. The DAC output rises one step per pulse. The counter stops when the DAC output just exceeds Vin, because the comparator output goes LOW, which disables the AND gate and signals EOC.

#### Given
- n = 4 bits, VFS = 12.00 V (DAC output for 1111)
- Clock PRF = 10 kHz, so T = 1/10 kHz = 0.1 ms

#### i) Maximum and minimum conversion time
- Maximum: the counter may have to go through all 2ⁿ − 1 = 15 counts.

```text
Tc(max) = (2ⁿ − 1) × T = 15 × 0.1 ms = 1.5 ms
```

- Minimum: one clock pulse (for a very small input).

```text
Tc(min) = 1 × T = 0.1 ms
```

(Some books count 2ⁿ pulses for the maximum, giving 1.6 ms.)

#### ii) Resolution
With VFS taken as the output for the full code 1111:

```text
Resolution = VFS / (2ⁿ − 1) = 12 / 15 = 0.8 V per step
```

In percentage terms: 1/(2⁴ − 1) = 6.67 % of full scale.

#### iii) Output for Vin = 4.25 V
The counter stops at the first count whose DAC voltage is greater than Vin:

| Count | DAC output (V) | DAC > 4.25 V? |
|---|---|---|
| 4 (0100) | 3.2 | No |
| 5 (0101) | 4.0 | No |
| 6 (0110) | 4.8 | Yes, so the comparator switches |

```text
N = floor(4.25 / 0.8) + 1 = 5 + 1 = 6
Tc = N × T = 6 × 0.1 ms = 0.6 ms
```

**Answer:**
- Tc(max) = 1.5 ms, Tc(min) = 0.1 ms
- Resolution = 0.8 V
- For Vin = 4.25 V: output count = 6 = **0110** (D3 D2 D1 D0), conversion time = **0.6 ms**

(If resolution is instead taken as VFS/2ⁿ = 0.75 V, the count is still 6, so the output and the 0.6 ms time do not change.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. When does a counter-type ADC stop counting?
   A. When the counter overflows
   B. When Vin equals zero
   C. After a fixed number of pulses
   D. When the DAC output first exceeds Vin
   Answer: D. The comparator goes low, disabling the AND gate and signalling EOC. (Key point: Stopping condition)

2. Maximum conversion time with 15 counts at 0.1 ms is:
   A. 1.5 ms
   B. 0.1 ms
   C. 0.6 ms
   D. 15 ms
   Answer: A. Tc(max) = (2^n - 1)T = 15 x 0.1 ms. (Key point: Maximum time)

3. Resolution with VFS = 12 V and 4 bits is:
   A. 0.75 V
   B. 0.8 V
   C. 1.2 V
   D. 3 V
   Answer: B. VFS/(2^n - 1) = 12/15 = 0.8 V per step. (Key point: Resolution)

4. Count and conversion time for Vin = 4.25 V:
   A. 5 (0101) and 0.5 ms
   B. 4 (0100) and 0.4 ms
   C. 6 (0110) and 0.6 ms
   D. 7 (0111) and 0.7 ms
   Answer: C. 5 x 0.8 = 4.0 V < 4.25 V, 6 x 0.8 = 4.8 V > 4.25 V, so stop at 6. (Key point: Count for 4.25 V)

## Related in Advanced Electronics

- [Count-up ADC numerical (VFS = 16 V)](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Acount-up-adc-16v-numerical) — Advanced Electronics, chapter 3
- [Dual slope ADC numerical (12 kHz clock)](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-numerical-12khz) — Advanced Electronics, chapter 3

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