--- title: "Dual slope ADC working; why accurate" subject: "Advanced Electronics" chapter: 3 key: "semester_4/advanced_electronics:dual-slope-adc-accurate" source: https://www.bctengineer.com/q/semester_4/advanced_electronics/dual-slope-adc-accurate site: BCT Engineering --- # Dual slope ADC working; why accurate Advanced Electronics · Chapter 3: Digital-to-Analog and Analog-to-Digital Conversion - Asked in: 2074 Chaitra, 7 marks; 2073 Shrawan, 7 marks; 2073 Chaitra, 7 marks (asked 3 times) - Video: [Dual Slope ADC: Basics, Structure, Working, Output, and Conversion Time](https://www.youtube.com/watch?v=wkQPFUHrrWA) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/dual-slope-adc-accurate - Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-3 ## Question Explain the working principle of dual slope analog to digital converter (ADC) with necessary circuit diagram. Explain why its output is accurate. ## Short answer The dual-slope ADC integrates the unknown input for a fixed time T1, then integrates a reference of opposite polarity until the integrator returns to zero; the counted time T2 gives N2=2^n·Vin/Vref. Accuracy is high because R, C, and clock frequency cancel, noise is averaged, and only Vref sets the result. ## Answer A **dual slope ADC** is an integrating ADC. It integrates the unknown input for a fixed time and then integrates a known reference of opposite polarity until the integrator returns to zero. The time taken in the second phase, measured by a counter, is proportional to the input. ```text S1 Vin --o\ R C o---/\/\/--+--||--+ -Vref -o/ | | +-(-) | GND --(+)>---+-- Vo1 --+ integrator | comparator (Vo1 vs 0 V) | clock --> [ control logic ] <--------+ | | switch S1 [ n-bit counter ] -> digital output ``` #### Working 1. **Reset:** the counter is cleared and the capacitor is discharged, so Vo1 = 0. 2. **Phase 1 (fixed time T1):** S1 connects Vin (positive) to the integrator. The output ramps down with slope −Vin/RC. The counter counts until it overflows after N1 = 2ⁿ clock pulses, so T1 = 2ⁿ·Tc (fixed). ```text Vo1(T1) = -Vin·T1/(RC) ``` 3. **Phase 2 (variable time T2):** at overflow the control logic switches S1 to −Vref and the counter restarts from zero. The output now ramps up with fixed slope Vref/RC. When Vo1 reaches 0 V the comparator changes state and the counter stops at N2. ```text Vin·T1/(RC) = Vref·T2/(RC) T2 = T1·Vin/Vref N2·Tc = N1·Tc·Vin/Vref N2 = 2ⁿ · Vin / Vref ``` The count N2 is the digital output and is directly proportional to Vin. ```text Vo1 0 +-. .--- | \ / | \ / | \ / | \ / | \ / | \ / | \ / | \ / | V |<-- T1 -->|<- T2 ->| slope -Vin/RC slope +Vref/RC (fixed) ``` #### Why the output is accurate - **R, C and clock frequency cancel:** they appear on both sides of Vin·T1/RC = Vref·T2/RC, and the same clock times both phases, so their tolerance, drift and ageing do not affect the result. Accuracy depends only on Vref. - **Noise rejection:** the input is averaged over T1, so random noise is reduced. If T1 is a multiple of the mains period (20 ms for 50 Hz), mains hum integrates to zero. - **Comparator offset** has little effect because the comparator only detects the zero crossing at the same level each time. - Good linearity, no missing codes, and high resolution are possible. The disadvantage is low speed (tens of conversions per second), so it is used in digital multimeters and panel meters. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In phase 1 of a dual slope ADC, what happens? A. Vref is integrated for a variable time B. Vin is integrated for a fixed time T1 set by the counter overflow C. Vin is integrated until the integrator reaches zero D. The capacitor is discharged Answer: B. Phase 1 integrates the unknown input for a fixed time T1 = 2^n Tc. (Key point: Phase 1) 2. What determines when the counter stops in phase 2? A. The counter overflows again B. Vin falls to zero C. The comparator detects the integrator output returning to 0 V D. The clock stops Answer: C. The reference of opposite polarity ramps the output back up to zero; the comparator then stops the counter at N2. (Key point: Phase 2) 3. The digital output N2 of a dual slope ADC is: A. N2 = 2^n x Vref/Vin B. N2 = 2^n x Vin x RC C. N2 = Vin/(RC x Vref) D. N2 = 2^n x Vin/Vref Answer: D. Equating Vin T1/RC = Vref T2/RC gives T2 = T1 Vin/Vref, so N2 is proportional to Vin. (Key point: Output relation) 4. Why are R, C and clock drift unimportant for accuracy? A. They appear on both sides of the equation and cancel B. They are made of precision parts C. The comparator corrects them D. They are measured and subtracted digitally Answer: A. The same RC and clock act in both phases, so only Vref determines accuracy. (Key point: Accuracy reason) 5. How can 50 Hz hum be rejected completely? A. Make T1 much shorter than 20 ms B. Make T1 a multiple of 20 ms so the hum integrates to zero C. Use a high-gain comparator D. Increase the clock frequency only Answer: B. Integrating a sine over whole periods gives zero. (Key point: Mains rejection) ## Related in Advanced Electronics - [Dual slope ADC; why quad slope is more accurate](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-quad-slope) — Advanced Electronics, chapter 3 - [Dual slope ADC block diagram; integral linearity](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-integral-linearity) — Advanced Electronics, chapter 3 - [Dual slope ADC: RC independence, noise immunity](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-rc-noise-immune) — Advanced Electronics, chapter 3 - [Dual slope ADC numerical (12 kHz clock)](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-numerical-12khz) — Advanced Electronics, chapter 3 - [Sigma-delta applications; 8-bit dual slope numerical](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Asigma-delta-dual-slope-numerical) — Advanced Electronics, chapter 3 ## Related in other subjects - [Working principle of analog spectrum analyzer](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Aanalog-spectrum-analyzer) — Communication Systems, chapter 1 - [Working principle of a digital telephone exchange](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Adigital-telephone-exchange-principle) — Telecommunications, chapter 4, asked 4× - [Digital vs analog communication; DCS block diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Adigital-vs-analog-dcs-block) — Communication Systems, chapter 1 - [Working principle of dc generator with diagram](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines%3Adc-generator-principle-diagram) — Electrical Machines, chapter 3