--- title: "Dual slope ADC block diagram; integral linearity" subject: "Advanced Electronics" chapter: 3 key: "semester_4/advanced_electronics:dual-slope-integral-linearity" source: https://www.bctengineer.com/q/semester_4/advanced_electronics/dual-slope-integral-linearity site: BCT Engineering --- # Dual slope ADC block diagram; integral linearity Advanced Electronics · Chapter 3: Digital-to-Analog and Analog-to-Digital Conversion - Asked in: 2071 Chaitra, 6+2 marks - Video: [Dual Slope ADC: Basics, Structure, Working, Output, and Conversion Time](https://www.youtube.com/watch?v=wkQPFUHrrWA) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/dual-slope-integral-linearity - Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-3 ## Question Draw the block diagram of Dual-slope type ADC and explain about its working principle with necessary diagram. Explain briefly about integral linearity of the DAC. ## Short answer Dual-slope ADC integrates the input for fixed time T1, then de-integrates with a reference until zero; the counter output N2 = N1 * Vin / Vref. Integral linearity (INL) of a DAC is the maximum deviation of the actual output from the ideal straight line after removing offset and gain errors, measured in LSB. ## Answer A dual slope ADC is an integrating ADC. It integrates the unknown input for a fixed time, then integrates a reference of opposite polarity until the integrator output returns to zero. The time taken for the second part is proportional to the input. #### Block diagram ```text Vin --o S1 C -Vref--o--+--[R]--+--------||--------+ | | (-)\ | >---------------+--Vo1-->[COMPARATOR] (+)/ | | v GND CLOCK-->[COUNTER]<-->[CONTROL] | digital out ``` #### Working 1. **Reset:** the counter is cleared and the capacitor is discharged (Vo1 = 0). 2. **Integration (fixed time T1):** S1 connects Vin. The integrator output ramps at a slope set by Vin/RC, while the counter counts a fixed N1 = 2ⁿ pulses. So T1 = N1·Tclk. ```text Vo1(T1) = −Vin·T1 / RC ``` 3. **De-integration (variable time T2):** when the counter overflows, it resets and S1 switches to −Vref (opposite polarity). The output ramps back towards zero at a fixed slope Vref/RC, and the counter counts again. 4. **Stop:** when Vo1 reaches zero, the comparator changes state and the control logic stops the counter. Then: ```text Vin·T1 / RC = Vref·T2 / RC T2 = T1·Vin / Vref, N2 = N1·Vin / Vref ``` The count N2 is the digital output. ```text |Vo1| | /\ (larger Vin: steeper up-ramp) | / \ | / \ same down-slope (Vref fixed) | / \ |/________\_____ t |<- T1 ->|| ``` R, C and the clock frequency cancel out, so the converter is accurate. Integration also averages out noise. It is slow (tens of ms) and used in digital voltmeters. #### Integral linearity of a DAC Integral linearity (integral non-linearity, INL) is the maximum deviation of the actual DAC transfer curve from the ideal straight line joining zero and full scale. It is measured in LSB or % of full scale, after removing offset and gain error. - Ideal: each output level lies exactly on the straight line Vo = D × LSB. - INL = max |Vactual(D) − Videal(D)|, for example ±½ LSB. - It is caused by resistor mismatch and switch resistance. A small INL means the output is proportional to the code over the whole range. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In a dual slope ADC, T1 is: A. Variable, T2 fixed B. Both fixed C. Both proportional to Vref D. Fixed, while T2 is variable and proportional to Vin Answer: D. Fixed T1 counts 2^n pulses; T2 ends at the zero crossing. (Key point: T1 and T2) 2. The output count satisfies: A. N2 = N1 Vin/Vref B. N2 = N1 Vref/Vin C. N2 = N1 Vin RC D. N2 = N1 + Vin Answer: A. From equal charge in both phases. (Key point: Relation) 3. Why is the dual slope ADC accurate? A. It uses 2^n comparators B. R, C and clock cancel, and integration averages out noise C. It runs very fast D. It has no reference Answer: B. Both phases use the same RC and clock. (Key point: Accuracy) 4. Integral non-linearity of a DAC is: A. Step-to-step change in size B. Time taken to settle C. Maximum deviation of the actual transfer curve from the ideal straight line D. Output with all bits zero Answer: C. It is expressed in LSB or % of full scale, caused by resistor mismatch and switch resistance. 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